A/DA Flanger does TZF?

[StephenGiles]

Yes indeed!

[analog kid]

 Hey all, monster progress on add on ideas to this thread since last I looked, maybe I'll regret etching and building (stock) from the sad layout?! You guys are mad scientists here , stuff way beyone me. My question is and sorry to break the stride here but you may see that I mentioned early in the thread that I for one had been long looking for a useable pcb layout using an SAD and was more than happy to take off building from the layout moos' hosted, low res and tight traces and all. though mine has many little tweaks (pads added, traces moved,etc... ) thanks to the clean up work of another forum member : ) so  It 's all populated and ready to fire up.       thing is and my question is since I'm sure I'm not the only who think the ADA is very much OK stock , though It seems noone has/is anyone else decided to attempt building from the existing layout? ( though I can see why those interested in building an ada would be holding for a pcb already done after seeing the optional mod ideas here and charlie's artwork)
I am sure that it's a working layout but It'd just be nice for me to hear if anyone else has/is building it from the existing pcb out there. 
apologies if I missed any posts or build reports : )  I just have to say that when the two threads started from Moos' posting the all inclusive ADA file stuff , I really expected quite a bit more "build in progress" chatter sparked from the sad pcb layout.
  Good stuff here though!

[oldschoolanalog]

Just want to catch up here. markus: Thanks for those great LFO sims. Your efforts are greatly appreciated.
Bounce is amazing. It's like a nuke. I'd rather have it, and use infrequently; than not have it after hearing it.

... aren`t bands useless when playing with effects?  

Many bands are useless when possesing musical instruments.
analog kid: If it's "all populated and ready to fire up"; PLEASE! Fire it up. I'll go out on a limb (no sawing, please...) and say more than a couple of us are VERY interested in your results! Out of curiousity, what technique did you use to put the artwork on the board?
Thanx,  Stephen and puretube for those great links and sound files.
And... Thanks again Charlie,for all the obvious reasons!

[StephenGiles]

I sure do appreciate your appreciation, pleased and proud and all that.

[analog kid]

 Well I used the same method I always use which is tone transfer via the ol' 'magic' photo gloss paper. I am lucky enough to have acquired a commercial Laser printer from a local plant that shut down which is a god send to my pcbing and diy efforts.   Also I shrunk this layout down EVEN SMALLER!! (the sad one in charlie's files) not as small as the new board you guys are getting done  but if you looked at how tight some of those areas were , and small, you can imagine how tedious the etch and post etch was to eliminate any bridges.  
So though everything looks good to go , you can imagine I am being very diligent about putting the SAD in the socket. making sure all else is hunkydory.  I do seem to be having an issue with the reg heating up to a fairly worrisome point.  Although I do have a couple of weak Regulators that I've been testing with that put out just over 14v (likely been overheated too many times ,btw does that cause regs to decrease rated output vltg, and get hot faster??) which may more likely be the reason for it more than any current draw problem in the circuit. 
I right now using the bridge rectifier uneccesarily with a 20v dc ps.  I had it running straight thru the reg first and tried the bridge just to see if it helped at all.  I will remove it and try again and maybe with another ps to see if there's an issue with it. but I see that (charlie) has added a diode in series with V+ on input side of the reg. Is that a +15v zener or something?   would adding a diode there help or be a good idea?           I obviously just wanna make sure that there's no major issues within the crkt before I pop that IC n and beging setting trims and/or troubleshooting.        Bottom line : Hot regulators always worry me ! but I realize sometimes they are just gonna be pretty warm. Its when Vout is dropping ,etc.. that I really hesitate.           apolgies for questions here about "just power up" but this is one to be cautious with! agreed?

[puretube]

heatsink?

[oldschoolanalog]

Are you using a 7815 ( 1amp/TO220 package) or a 78L15 (100ma/TO92 package) for your V reg?

[oldschoolanalog]

Diode = Polarity protection(in this case)

[analog kid]

Are you using a 7815 ( 1amp/TO220 package) or a 78L15 (100ma/TO92 package) for your V reg?

I often wonder when a 1A may be better than 100ma for a crkt or is the choice better based on the actual PS running into it?  I typically use 1A 220 type in ANY situation where I'm having trouble with them getting too warm.
the only new reg I have is a 100ma TO92's and it seems that it's not getting more than warm now and giving me a good 14.95v and not dropping more than a couple tenths , where the couple of old regs that I have (likely overheated too many times) the out vltg is low to start and steadily drops very slowly. Is this something they do once they've been "abused"? Lose ability to hold output voltage up. If so then I probably just have a couple of weak regs as I expected and am good to go on getting the ADA up and running.   

Diode = Polarity protection(in this case)

Far as the layout Charlie is working on and what I was referring to, I don't think so. (?) this looks to me to be a series connect didoe in line with V+ from ps. (apologies if I'm mistaken)  I have seen zeners(value of crkt's V+ requirement) use in this manner as 'current limiter' I believe, so I thought maybe that's what he was intending there, rather than polarity protection?  I'd like to know regardless as I'm likely going to pull that bridge rectifier in the end and power directly through the regulator. any extra stability or protection is nice in a crkt like this.
Mine IS passing signal but no flanging or pots doing anything yet , BUT I have just now popped in the SAD , first being sure that the crkt was getting good +15v, with No or minimal problems. Now that seems to be the case I am READY.
Just to put my mind at ease can someone tell me if the SAD vltgs I'm starting with look at all in order or no Red Flags at least? not sure they do but I've not really checked them over the schem yet. I'll do that now.    Thanks everyone
1-  0             16-  0
2-  4.7          15-  4.7v
3-  7.2          14- .05 ??
4-  0             13-  0
5-  2.6          12-  2.6
6-   0           11-  14.9
7-  14.9        10- 7.2
8-  0            9- 13.9
 

[analog kid]

 ok question, It looks like we've located an error in the sad layout ( Gripp actually gets the credit for noticing it I should say)  when compared to the sad modded schem.  Just to make it known IF incorrect and verify
Pin 10 coming from the 4047 should connect to Pin 7, NOT 6 as it's drawn , on the 4049, correct?  that clock signal is going to pins 6, 9, and 11 on 4049 when it should Not if this is the case. I'm going to go ahead and make this change to the pcb and give it a go but i'm sure another opinion is always good. checked against the IC's data sheet it seems it should be pin 7 as well'
thanks
Also on the regulator question. I AM getting stable Vout from a 100ma and no longer getting even very warm HOWEVER I just noticed something strange. I am still getting a reduced vltg at the Vin of the reg from what my ps is supplying!  ie; ps outputing 20.5v is turning into 18.5 or so at the regulator.   Bear in mind I still have the bridge rectifier arrangement in place running dc to the ac1/2 pads. I haven't pulled the diodes back out yet before noticing this. And I have a 1000uf 25v in for the initial V+ filtering.          should this be alarming to me, since the reg is NOT getting warm?

[oldschoolanalog]

The FWR is responsible for the V drop. The Irwin/Giles schem shows pin 10 of the 4047 feeding pin 7 of the 4049. Pin 6 of the 4049 is an output.

[analog kid]

 Ok , first off I really didn't mean to take over this post. Honestly but I hope my posts/questions "apply" and hope to give you all my results with the layout.
I think I may be alright w/ the reg issue now, although i believe I'm gonna need to go with 1A (not sure what this thing's gonna draw) because it is still getting near hot after several minutes. so hope all power issues are ok.

The Irwin/Giles schem shows pin 10 of the 4047 feeding pin 7 of the 4049. Pin 6 of the 4049 is an output.

yes indeed, and this seems it should be this way looking at the data sheets. But if you take a look at the SAD pcb layout in the ADA files you will notice that Pin 10 is routed to PIN 6  of 4049!  I rerouted this trace (siding w/ the schem as correct) and my SAD vltgs obviously changed and seem to be more correct now. they are now as follows:
  1-  0              16-   0
2- 9.5            15-    9.6
3-  7.2           14-    7.7v
4-  0              13-   0
5-  7v            12-     7.2
6-  14.9         11-     14.9
7-  14.8         10-     7.2
8-  7.6           9-     13.9

[puretube]

...
Pin 10 coming from the 4047 should connect to Pin 7, NOT 6 as it's drawn , on the 4049, correct?

you`re right, IMHO the current preliminary layout is wrong, here.

[StephenGiles]

The voltage at pins 8 & 14 of the SAD1024 should be exactly the same - difficult to measure without 2 meters! I dare say the voltage will fluctuate slightly during the time you move the probe between the 2 pins. A good sign that all is well with the BBD clock is that the voltages on the 2 separate clock lines are near enough the same.

What would happen if say the clock to pins 3 & 10 was modulated through one of the OR gates of a 4030 or 4070 on the way?? Presumably the waveform would not be acceptable to the SAD - has this been considered before I wonder?

[puretube]

thought about that a long time ago, and even made a note to ever check that out...

probably it would decrease the S/N ratio.

[moosapotamus]

Pin 10 coming from the 4047 should connect to Pin 7, NOT 6 as it's drawn , on the 4049, correct?

Good catch. Thanks!

I see that (charlie) has added a diode in series with V+ on input side of the reg.

I'm planning to power this from an 18VDC supply (DC Brick or wall wart), so I intended the diode to be for polarity protection.

~ Charlie

[analog kid]

While we're talkin here, any opinions on a FET other than (2n4393) that oughtta work fine here??  Lookin at it's function in the circuit it seems to me it's gonna be pretty important and in the way of N-channel I only have more usual suspects in my bin( 545x, 5952, J201 .. ) would one of these choices likely be a good choice for the job?  I realize the original used an SDG pinout.   I did find ONE fet out of the few I auditioned that gave me a very 'harmonic' distortion ,though no sweep became apparent I did take this to believe this was probably the correct fet choice since it was the only one that gave me anthing othen than a clean signal    My sad vltgs are seeemingly good and lfo seems to be functioning based on it's pin 1,3,7 cycling vltgs.
One issue is I notice I am getting some clean signal bleeding through when no power is applied so I am optimistic I have a 'simple' error somewhere in the audio path.  : )  I am just hoping that the layout is mistake free aside from the one misrouted IC pin. I worry there could be more 

[analog kid]

Well for anyone who care to know I DO have my ADA up and running from the sad layout (with changes mentioned previous) The lfo / clock is functioning normal and it's flanging although i've not got the auto sweep adjusted well enough yet. I have the noise gate disonnected right now for troubleshooting purposes and avoid FET issues but may connect it back now.  BBD is biased under 6v , a note to builders, the 10k (R13) resistor being changed to 4.7k going to ground off T1 bias pot seems pretty crucial (might differ with pot but...) as I couldn't voltage to bias into a low enough range til i made that change.

I believe I have a problem within IC1(b) based on the problem described below and vltgs I'll list, I'd love to hear any opinions on this.  (Mr Giles, other ADA builders?)

Pins 5,6,7 all bias with T1 and while the vltgs all bias appx the same, when probing here all three react with the Enhance pot rotation, increasing volume/feedback (but to different extents)  Pin 7 being the only of the 3 that will pass signal with Enhance pot off The others Pin 5 and 6 WILL NOT pass ANY audio at all unless Enhance is turned up, which reacts as a gain for all these pins. Pin 6 by far the most sensitive to this interaction, going into complete earspltting feedback much sooner in the rotation.
   Shouldn't Pin 7 Not show any signal UNTIL signal is present at pin 5,6?
The votages are as follows w/ T1 set for 6.02 bias ( these vltgs are taken at same time not fluctuations)   IC1/2 are OPA4131PA quad fet input , TL074 give same vltgs IIRC
1   7.18       14   7.18
2   7.18       13   7.18
3   6.53       12   7.12
4   14.3       11     0
5   5.97v      10  7.18
6   6.02v      9   7.18
7   6.02v      8   7.18
also should pin 3 not be dropped like that
thanks again

[Gripp]

OK, I'd better post too as I feel I have something to do with all of this.
Analog kid was given a cleaned up version of the Mike I SAD mod layout (rev3 audio path, mods to accommodate SAD, noise gate still there etc; NOT the same as the Irwin/Giles schem). He then shrunk the layout some more. I just cleaned up the artwork and corrected some errors but being the slow builder that I am, analog kid has been miles ahead in terms of actual building. So we've been troubleshooting a bit, thinking a lot..etc.

Just wanted to point out that the voltages and thinking about IC1 in the post above pertains to a stock rev3 input audio section except for R13 being changed from 10k to 4k7 to make the bias range better for the SAD. The noise gate is completely disabled by lifting J13 and J5, shorting out R34 and removing Q1.

I too still don't exactly get how the feedback loop and diode limiting works in the rev3. Sorry that no schem is linked to. I haven't seen a public rev3 schem so...

If anyone wants my cleaned up artwork just ask. I can't host it and I can't answer a million mails either so if there's great interest maybe someone can help. Moosapotamus seems to be the guardian of all files ADA?

Best!
Pelle G

[StephenGiles]

I have no idea what your problem might be with IC1B apart from an error in the pcb layout. Have you tested "as you build" as I did on my veroboard version - a must in my view for this type of circuit, or did you stuff the whole board first?