The delay time is more linear than you think!

Some time ago I decided to tackle this question. First, I tried to think how to setup an internal clock with an external resistor (in a generic way). Probably a resistor sets a control current that charges a cap with a ramp, I thought, and this method is pretty linear. Let's see: at almost 0 ohms you have 31.3ms delay; let's find which resistor value doubles said figure. Ah, it's 2.8k which produces 61.6ms.

Hypothesis:

The PT2399 has an internal 2.8k resistor that adds to the external resistor, and delay time is set linearly according to the sum of the internal+external resistors.

Proof:

Let's see which resistor value triples the minimum delay. Triple delay is 93.9ms. From the published table we see Rext is a value slightly above 5.4k.

On the other hand, theoretical resistor value would be 3*2.8k = 8.4k, minus the 2.8k assumed internal resistor, one gets: Rext'=5,6k. Pretty close so far, but could be diverging, so let's see one more case.

Let's consider 11 times the base delay, or 11*31.3ms=344.3ms, pretty close to 342ms that has an associated Rext=27.6k. Now, the theoretical Rext, or Rext'=11*2.8k-2.8k = 28k, which again is very close to 27.6k.

In summary, for the minority who might still be awake after the above explanation, you can consider the delay time directly proportional, or linear to the external resistor plus an internal resistor of 2.8k (AKA stopper resistor).

P.D. It is possible to graph Rext v/s the delay time in Excel or Calc. It is easy to notice a straight line is a very good fit for the points, but it intersects the Y-axis near -2.8k, the internal fixed resistor.