CD4046 VCO Math

[nelson]

Hi folks,

I have spent hours staring at datasheets for the 4046, but I still can't find out the math for working out R1, C1 + R2 as they relate to center frequency, minimum and maximum frequency of the VCO. The datasheets have graphs, but I would rather know the formulae before I hit the breaboard.

Does anyone have any links or resources for design tips on utilising the 4046 as a VCO or am I left with ball park values, breadboard tweaking and warming my oscilloscope up?

[alanlan]

I'm not sure there is a reliable formula.  I used the graphs and obtained reasonable results.   I think the frequency is supply dependent anyway.

[Mark Hammer]

Don't know if it will help, but I posted this some time back: http://hammer.ampage.org/files/Marston%27s4046circuits.PDF

[gez]

Info from Practical Oscillator Circuits by A Flind:

R1 from pin 11 to ground
R2 from pin 12 to ground
C1 from pin 6 to 7

R1 sets Max frequency
R2 sets min frequency and is not essential. "However, as it produces a constant frequency increase right across the control range, it is easier to think of it as a positive frequency 'offset'.  For instance, if the circuit was arranged to operate over the range 0 to 20 kHz with R1 and C1, adding a resistor from pin 12 for a min of 5kHz will alter the range to 5 to 25 kHz.

C1 can be any value from 50pF upwards, but can't be polarised.

"The output frequency is reasonably linear with the control voltage, although there is some deviation below about 20% of the supply."

Best regulated for consistency, as frequency is supply dependant:

"With a supply of 10 Volts a reasonable starting point would be: f = 2/(CXR)"

To calculate 'offset' use R2 value in above formula.

Buy this book if you can.

[gez]

Further info from Practical Electronic Design Data by Owen Bishop:

R1 must be between 10K and 1M

C must be greater than 50pF (add 32pF for input capacitance with low values of C).

At 15V, frequency-voltage curve flattens towards lower end of range.  Below 2V, is pretty non-linear (unreliable).

There are more accurate calculations for R2 (too much to post here...and anyway, it's all ball-park stuff).

Definitely buy this book if you can!

[nelson]

Thanks guys.

That pdf is really helpful Mark. It does go into a bit more detail than the datasheets I've read, especially in different applications to limit Fmin + Fmax. The VCO inhibit pins are also a handy hint for getting a simple A/DA flanger style clock gate.

I get the relationship between the components and that frequency is somewhat dependant on VDD. However it would be nice to be able to design with as close to certainty as possible.

I'm hoping to get the fundamentals of the VCO down as a universal BBD clock for Delay, flanging and chorus designs.

I can't even find a decent LTspice model of the 4046.


Looking at the datasheet:

Center F = (Fmax-Fmin)/2+Fmin @ 0.5Vdd

Vdd=9v

Say I want a max freq of 90Khz and a minimum of 7Khz.

Center F = (90K-7K)/2+7K

Center F = 48.5Khz

Going to the graphs on the datasheet here

http://www.datasheetcatalog.org/datasheets/400/109068_DS.pdf

Figure 4

Center Freq when R2=Infinite

C1 = 1n

R1 = Around 820K

Then adding an offset via R2, in fig 6

If C1 = 1n

Then R2 = Around 2m2-4m7?

Again, the graph isn't very clear.

To get an offset for fmin=7Khz

This pushes Fmax to 97Khz,


I'm a tad confused.

It would be nice to have a formula.

[nelson]

Further info from Practical Electronic Design Data by Owen Bishop:

R1 must be between 10K and 1M

C must be greater than 50pF (add 32pF for input capacitance with low values of C).

At 15V, frequency-voltage curve flattens towards lower end of range.  Below 2V, is pretty non-linear (unreliable).

There are more accurate calculations for R2 (too much to post here...and anyway, it's all ball-park stuff).

Definitely buy this book if you can!

Further info from Practical Electronic Design Data by Owen Bishop:

R1 must be between 10K and 1M

C must be greater than 50pF (add 32pF for input capacitance with low values of C).

At 15V, frequency-voltage curve flattens towards lower end of range.  Below 2V, is pretty non-linear (unreliable).

There are more accurate calculations for R2 (too much to post here...and anyway, it's all ball-park stuff).

Definitely buy this book if you can!

This is really great!

I have more to work from now.

Thanks Gez!

Does that mean the linearity of the response can't be relied on +20% from VSS and -20% from VDD?

So, for a 9 volt supply the CV must be between 1.8v and 7.2v?

So, I then need to work out a different center frequency to ensure linearity over the desired frequency range.

Ok, this is becoming far clearer.

[gez]

Personally, I don't bother with R2.  I choose R1 so that the oscillator's range is slightly above required max frequency.  That tends to keep most of the useful range above the non-linear point.

[gez]

Does that mean the linearity of the response can't be relied on +20% from VSS and -20% from VDD?

It's only the lower 20% (rough guide) of the control voltage range where linearity goes pear-shaped.  Everything above (right up to VDD) should be nice and linear.

[gez]

Personally, I don't bother with R2.  I choose R1 so that the oscillator's range is slightly above required max frequency.  That tends to keep most of the useful range above the non-linear point.

PS. If driving the control pin with an LFO, you may have to change bias point of said LFO (upwards) in order to keep things linear.

[nelson]

Does that mean the linearity of the response can't be relied on +20% from VSS and -20% from VDD?

It's only the lower 20% (rough guide) of the control voltage range where linearity goes pear-shaped.  Everything above (right up to VDD) should be nice and linear.

I suppose it's simpler to design the CV with a ~ 20% + Vss DC offset than it is to futz around with R2.

Seeing as to ensure linearity you have to include the dc offset even with R2.

Thanks a lot for your help Gez.

[George Giblet]

I did my own investigation on the 4046 some years back and worked out formulas and the control voltage behaviour.  I can't find the notes in my big pile of stuff in a short space of time.   

Here's a few things I seemed to remember,

-  Ballpark formula is T = 0.5*RC and then f = 1/T.  So,
             fmin ~ 1/(0.5*R2*C)
       and fmax ~ 1/(0.5*R1*C);               I can't remember if R2 affected fmax.
 
      As the data sheet graphs indicate the actual values depend on R and the supply voltage.

-  The points where the control voltage becomes non linear weren't percentages of the voltage rail.
    They were more fixed voltages from the rails.  IIRC it is fairly non linear at about 1V from ground and about 0.7V from the +V rail.

There was some 4046 PLL software from Philips around, it was DOS software.   It was mainly used to select parts for a proper PLL control loop operation and computed the loop filter components.   You might want to check it out it *may* have an accurate calculator for the oscillator values.

[nelson]

I did my own investigation on the 4046 some years back and worked out formulas and the control voltage behaviour.  I can't find the notes in my big pile of stuff in a short space of time.   

Here's a few things I seemed to remember,

-  Ballpark formula is T = 0.5*RC and then f = 1/T.  So,
             fmin ~ 1/(0.5*R2*C)
       and fmax ~ 1/(0.5*R1*C);               I can't remember if R2 affected fmax.
 
      As the data sheet graphs indicate the actual values depend on R and the supply voltage.

-  The points where the control voltage becomes non linear weren't percentages of the voltage rail.
    They were more fixed voltages from the rails.  IIRC it is fairly non linear at about 1V from ground and about 0.7V from the +V rail.

There was some 4046 PLL software from Philips around, it was DOS software.   It was mainly used to select parts for a proper PLL control loop operation and computed the loop filter components.   You might want to check it out it *may* have an accurate calculator for the oscillator values.

Thanks George.

I have the DOS software, unfortunately it only goes to a VDD of 5v. There's also a java based calculator, however it only goes to a vdd of 5v and expects frequencies well into the megahertz. These digital logic guys get all the fun toys. The calculators are for the higher frequency 74hct4046, which has an absolute max Vdd of 6v. I want to get as much headroom as possible out of the bbd's so the low Vdd is no good. I may change my mind if the run of the mil Cmos 4046 craps out before I get a *really* wide flanger sweep and switch. I doubt that will happen though. The ultraflanger manages a 50K to 1.1Mhz sweep with the 4046.

I have a preliminary clock section for a 2X3205 Chorus/Vib/Delay going. I will just need to breadboard it to make sure the VCO isn't way out of the ballpark. I'm going to trim R2 to squeeze as good a fidelity and long delay time out of the BBD's as possible anyway. What good's a delay without a clock trim . 

I did think that the vco became non-linear close to Vdd.

Breadboarding will confirm.

R2 pushes up Fmax by whatever you set Fmin to, AFAICT.

[gez]

R2 pushes up Fmax by whatever you set Fmin to, AFAICT.

Going by memory here, but R1 acts as a stop resistor.  It's in series with an internal voltage controlled resistor.  The amount of current that flows through this resistance chain to earth determines the frequency of oscillation.  With 0V control voltage the VCR is off, no current flows and the oscillator shuts down.  All R2 does is shunt the internal VCR, so it prevents the oscillator form turning off and provides a min frequency of oscillation.  With its inclusion, there is an additional current path to earth, which creates an offset.  It's possible to run the oscillator with only R2, although its frequency will be totally fixed (no voltage control).

[nelson]

Thought I'd end this thread with a "money shot". I got time to breadboard the VCO and play with it.


A simple 4096 stage bbd voltage controlled clock for delays.





Fmax= ~100Khz

Fmin= ~ 5Khz


Minimum frequency adjustable by the clock trim.



Here's the unconfirmed delay design.

I'm going to add full wet/dry blend and change the LFO before I finalise the board.

A lot of it is borrowed from other well known delays, you could say it has way huge filtering.




Thanks to everyone in the thread for their tips!

[snap]

Two BBDs in parallel mode?

[nelson]

Two BBDs in parallel mode?

Haha! woops.

Well, that's obviously wrong. They are meant to be in series.

Thanks for pointing that out. I should probably stop drawing schematics in the wee hours of the morning.


Schematic updated, BBD's now in series.

[ExpAnonColin]

Hey Nelson, just FYI - in my twiddlings with CD4046 and 3205's, I found them unable to drive more than one BBD.  You're going to either need to boost the clock outputs with transistors or use 3102s.  Unless you found something different... I was just experiencing unacceptable distortion.

-Colin

[TELEFUNKON]

Anyone read through this appnote until page 45? http://www.etc.tuiasi.ro/cin/Downloads/pll/PLL-4046.pdf

[R.G.]

Hey Nelson, just FYI - in my twiddlings with CD4046 and 3205's, I found them unable to drive more than one BBD.  You're going to either need to boost the clock outputs with transistors or use 3102s.  Unless you found something different... I was just experiencing unacceptable distortion.

+1. The clock inputs of BBDs are usually not buffered, for some reason I can't fathom (back to this later). The capacitance can be as high as three to four nanofarads, which is huge for a logic input. The clock/driver chips have both an oscillator and big-current drivers for the outputs. You can use 3102s, transistors, or put in a CD4049B (for buffered) chip and use three and three of the sections to drive the two clock phases. The 4049 is designed as a high current driver, a many kind of inverter. 

As for the fathoming, it has always made me wonder what they were thinking when they split out drivers from the delay array. That's not the kind of signal you want to run across a PCB if you're doing chip design. High speed clocks are hard enough without also making them be high power. It can't be that they didn't think of it - the guys at Reticon even showed them how, with the SAD512d and its integrated flipflop and drivers. It's bad practice to require high speed/high power clocks on ICs unless you just can't do anything else. Seems like they could have found the dozen or so gates to do this in an array with 8000 or more MOS devices already there.