Thanks guys.

That pdf is really helpful Mark. It does go into a bit more detail than the datasheets I've read, especially in different applications to limit Fmin + Fmax. The VCO inhibit pins are also a handy hint for getting a simple A/DA flanger style clock gate.

I get the relationship between the components and that frequency is somewhat dependant on VDD. However it would be nice to be able to design with as close to certainty as possible.

I'm hoping to get the fundamentals of the VCO down as a universal BBD clock for Delay, flanging and chorus designs.

I can't even find a decent LTspice model of the 4046.

Looking at the datasheet:

Center F = (Fmax-Fmin)/2+Fmin @ 0.5Vdd

Vdd=9v

Say I want a max freq of 90Khz and a minimum of 7Khz.

Center F = (90K-7K)/2+7K

Center F = 48.5Khz

Going to the graphs on the datasheet here

http://www.datasheetcatalog.org/datasheets/400/109068_DS.pdfFigure 4

Center Freq when R2=Infinite

C1 = 1n

R1 =

*Around* 820K

Then adding an offset via R2, in fig 6

If C1 = 1n

Then R2 =

*Around* 2m2-4m7?

Again, the graph isn't very clear.

To get an offset for fmin=7Khz

This pushes Fmax to 97Khz,

I'm a tad confused.

It would be nice to have a formula.