And, just for fun, here is some code I wrote a while ago that creates a delay based on the high time of one POT input (no s/w debounce, the input was from a signal generator but could be a switch with some debounce on it) + the voltage on another POT input. Could use the final count for many differnt things (a delay as in this case, the coefficient for LFO frequency or amplitude, reverb length, etc.)
;delay time controlled by high time of a square wave+POT
;Frank Thomson
;OCT Distribution (310)348-9626
;
;pot1 adjusts delay by voltage
;pot2 adjusts delay time based on high time of a square wave input
;total delay is sum of pot1 and pot2
equ length 32767
equ sdel 0x03ffff ;start up delay, 4 sec. at 32K sample rate
mem echo length ;echo delay
equ countval reg0
equ pot2fil reg1
equ sigval reg2
equ thiscount reg3
equ totaldel reg4
equ pot1fil reg5
equ delreg reg6
; Clear register on start
skp RUN, loop
clr
wrax countval, 0
wrax pot2fil, 0
wrax sigval, 0
wrax thiscount, 0
wrax totaldel, 0
or sdel
wrax delreg, 0
loop:
; Only look at POT2 input if we have timed out the start-up timer
sof 0,0
rdax delreg,1.0
skp zro,gopot ; if counter is 0 do the stomp pot routine
sof 0,0 ; else clear ACC
or 0xffffff ; load -1 into acc
rdax delreg,1.0 ; delreg - 1
wrax delreg, 0 ; write delreg and clear acc
skp zro, govar ; go to the variable pot routine
gopot:
; If signal is > 0.5, increase counter
sof 0,-0.5 ; Load -0.5 into ACC
rdax pot2,1.0 ; POT0 - 0.5
skp neg, siglow ; If < 0 then skip over following
; If here then the signal is high
; Was the old signal high?
clr ; Clear ACC
rdax sigval, 1.0 ; Read old signal
skp gez,lbl2 ; If old signal was high, skip the following else clear counter
clr ; 0 -> ACC
wrax countval,0 ; 0 -> counter
lbl2:
clr ; Clear ACC
or 0x000100 ; "1" -> ACC - normally would be 0x000100, may want to double it
rdax countval, 1.0 ; counter + 1 -> ACC
wrax countval,0 ; ACC -> counter
skp zro, outit ; At this point we have a high signal and have incremented the counter
; Skip over low signal routine and do the delay
; Signal low routine
siglow:
clr ; Clear ACC
rdax countval, 1.0 ; Read counter value
wrax thiscount ,0 ; Write it to the register used in the delay calculations
outit:
; At this point, thiscount contains the number of sample to delay
; Save wave value
sof 0,-0.5 ; Load -0.5 into ACC
rdax pot2,1.0 ; POT2 - 0.5
wrax sigval, 1.0 ; Save the current signal value
; Make sure total delay is less than delay length
govar:
clr
or length*256
mulx pot1 ; POT1*length -> ACC
rdax thiscount, 1.0 ; Add in the count
wrax totaldel,0 ; Save the total delay, clear ACC
or length*256
rdax totaldel,-1.0 ; length - totaldel
skp gez, goout ; if >=0 then totaldel < length so OK
clr
or length*256
wrax totaldel,0
goout:
; Smooth value
clr
rdax totaldel, 1.0 ; Load delay into ACC
rdfx pot2fil, 0.000125 ; Smooth it : (target - current) * C + current
wrax pot2fil, 0 ; Save it
;
rdax adcl, 1.0 ; Get left input
wra echo, 0 ; Write it to the head of the delay
;
or echo*256 ; Load base of delay into ACC
rdax pot2fil, 1.0 ; Get the value, it is the left delay tap to read
wrax addr_ptr, 0 ; Write it to the address pointer register
rmpa 1 ; Read from memory - left
wrax dacl, 0 ; ACC-> DACL
