OK, thanks guys for your interest - I did made just two small changes to
original schematic (renamed to v1.0a now), schemo above should be now actualised (v0.1, 10.8.2009 - you may need to refresh this page to overrule your browser cache). 1st change is about separating of V
CC for BBD part and clock buffer part (to allow bi-wiring or other approaches for better power filtering), 2nd is about R3 value set from 13k9 to 14k (it's the best value for this resistor and good suplier should have it in stock, it's
E48 standard). I did created PCB layout based on this updated schemo, and juancra is about to verify it - right, Seb? How did exam go?
About GGG DEM: this retrofit should fit there nicely as well (MN3007 should even profit from those 15 volts there). No values have to be changed, only 15+ volts capacitors have to be used - connections would be:
| GGG/DEM | Retrofit |
| A | VCCb |
| B | VCCa |
| C | CLK+ (or CLK-) |
| D | CLK- (or CLK+) |
| IC3, pin 2 or 15 | IN |
| IC3, pin 6 or 12 | OUT |
| GND | GND |
Only change necessary on GGG board would be halving clock capacitor C17 and of course proper bias and gain adjustment (bias adjustment remains principially same, for gain adjustment divider made by R12 and R13 could be used*).
Only change on retrofit board would be not loading of C3 (there's no LPF applied directly to SAD's output on GGG's DEM, so retrofit should not do it either). Anybody willing to try?
T.
* if the unity gain (R12=min, R13=max) was not enough, lowering of R14 would allow to achieve required boost.
