There is a certain level of complexity which you can't dip below, when it comes to noise control, unless you subcontract all the complexity out to a dedicated chip designed to do it. You will always need some attenuation element, whether FET or optoisolator, or OTA, and you will always need a rectifier to track the input signal, and you will always need some sort of gain stage to drive the rectifier. Everything beyond that is simply bells and whistles to make each element behave better
The Japanese schematic I posted is actually not all that complicated or exotic. The 2SC1000 trannies can be subbed with 2N5088s (watch out for the pinout differences), the 1S1555s can be 1N914s, and the LM324 can be a TL074 without any problems arising (though this would not improve performance in any way). The Zener is just any old 5.1V zener, and the K30A is reasonably available, though you can probably sub a 2N5457 for it if you need to.
The JFET is used as a voltage-controlled resistor, in parallel with the 470k fixed resistor. Between their combined parallel resistance, and the 10k resistorin the signal path just ahead of them, they form an attenuator/voltage-divider. When the JFET is turned on, the combined parallel resistance of the JFET and 470k drops, and they attenuate the signal. The extent to which the signal is attenuated is a function of the 10k and 470k resistors. If the 470k is decreased to, say 220k, then the drop in combined resistance produced when the JFET goes low is not that big a change from the resting state. Same thing if the 10k resistor is increased to 47k. If that "input leg" of our virtual pot has a greater resistance, then the "ground leg" formed by the 470k and JFET has to drop wayyyyyy down to produce a big change in attenuation. Conversely, if we change the 10k to 2k2, then it will take a huge change in JFET resistance to produce dramatic attenuation.
All of this is to say that you can tinker with the amount of attenuation produced by playing with either the value of the 10k, the value of the 470k, or both.
Much like the Dynacomp/Ross compressor, and all variants, the 1M Decay pot over on the right determines how long it takes to recharge that 10uf cap. Large series resistance between B+ and the + end of that cap means that current trickles in, rather than rushes in, so it takes longer to recharge the cap. The JFET is set to low resistance (i.e., the signal is "gated" off) when that cap is fully charged. So, the slower the recharge time, the longer the signal hangs around before the circuit cuts it out completely.
A gate with a variable decay time, and adjustable attenuation, will provide reasonably satisfactory performance over a fairly broad range of circumstances. If the threshold control is .twitchy", then let us know and some component-value adjustments can be made to improve the dialability.
Finally, please note that when I scanned the project article, I made no attempt to assure the scale. Plus, the layout is not flipped around in anticipation of PnP. You will likely have to do a screenshot of the layout, and then flip it over and resize, in whatever your graphics application of choice happens to be, before committing to a toner transfer.