"Sonic Death Ray" Phaser - a phase insurrection!

[frequencycentral]

......ah, screw this puny 6 stage malarkey, after seeing Strategy's Tau Pipe phaser I'm gonna make this bitch with 16 stages and 12 regen taps.........!

[Brymus]

Heck Yeah !!!

[slacker]

To be honest I'm trying to ruffle any feathers. I'd really like to hear a short explanation about getting around the idea of having to use matching FETs for things like Phase 45. Which is what I thought Eb+7 was getting at.

Here's the appnote JC was talking about, or I presume it's this one anyway.

http://www.alldatasheet.net/datasheet-pdf/pdf/161774/VISHAY/AN105.html

I've only read it once, so it hasn't all sunk in yet I get the bit about the resistors reducing distortion. but I don't yet see how the information relates to the need or otherwise to match FETs.

[panterafanatic]

I for FETs, the only thing I've got is apparently 2N5457s, are these close enough to the 2N5485s? (Edit: I'll just test it out now and find out.)

I also do not know how to match the FETs.. Do I check for leakage or hFE?  

[frequencycentral]

I for FETs, the only thing I've got is apparently 2N5457s, are these close enough to the 2N5485s? (Edit: I'll just test it out now and find out.)

I also do not know how to match the FETs.. Do I check for leakage or hFE?  

I did try some 2n5457, which produced clicking/thunking. They were not matched, or even measured. When I get time I'll measure and match them and try them.

For FET matching see the link to the GEOFEX matching fixture on page 1.

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I'm now thinking of making this a modular design, with the LFO and input stage on one board using a NE5532, together with the speed and regen pots. Then I'll design a layout for a 4 stage board using a TL084 and four FETs, with pads to add as many additional 4 stage board as desired. How cool is that?

To be honest I'm trying to ruffle any feathers. I'd really like to hear a short explanation about getting around the idea of having to use matching FETs for things like Phase 45. Which is what I thought Eb+7 was getting at.

Here's the appnote JC was talking about, or I presume it's this one anyway.
http://www.alldatasheet.net/datasheet-pdf/pdf/161774/VISHAY/AN105.html
I've only read it once, so it hasn't all sunk in yet I get the bit about the resistors reducing distortion. but I don't yet see how the information relates to the need or otherwise to match FETs.

Shame on you for only bothering to read it once. Don't come back until you've read it the other 99 times.    I'm so clever I might only have to read it 50 times........

[slacker]

I'd of thought by now you'd just have this stuff jacked straight into your cyborg brain box.

[stringsthings]

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I'm now thinking of making this a modular design, with the LFO and input stage on one board using a NE5532, together with the speed and regen pots. Then I'll design a layout for a 4 stage board using a TL084 and four FETs, with pads to add as many additional 4 stage board as desired. How cool is that?

sounds very cool ....

but wouldn't the regen pot go on the same board as the FETs and the TL084?

[Strategy]

attaboy frequencycentral! 

......ah, screw this puny 6 stage malarkey, after seeing Strategy's Tau Pipe phaser I'm gonna make this bitch with 16 stages and 12 regen taps.........!

[doc_drop]

Just to report in on my breadboard progress...

I have it up and phasing, but it is a very uneven phase. I think I must not have a stage going or something? If I turn up the Mix knob it gives me a tremelo since there is no sound during part of the cycle.

I used 2N5485's, but I made no attempt to match them. That might be part of the problem.

Anyway, I'll report back if I make any progress. Maybe I just need 16 stages!

[frequencycentral]

When the LFO output voltage is most positive, you're almost certainly forward-biasing the JFETs.  I would either shift the audio portion's bias more positive, or the LFO's bias more negative (or both!), to try and reduce distortion while increasing the range of the sweep.

Thanks Alex, that really worked well. the LFO bias voltage divider is now 220k/150k (the 150k to ground), much wider sweep - very, very nice. The LFO was previously 'topping out a little', this has totally cured it.

Just to report in on my breadboard progress...

I have it up and phasing, but it is a very uneven phase. I think I must not have a stage going or something? If I turn up the Mix knob it gives me a tremelo since there is no sound during part of the cycle.

I used 2N5485's, but I made no attempt to match them. That might be part of the problem.

Anyway, I'll report back if I make any progress. Maybe I just need 16 stages!

PM'd!

[frequencycentral]

What surprises me is that even 2 stages apart sounds really good. The four regen modes really do make it sound like four different phasers, some low and bass heavy, others stratospheric.

My mistake. I'm using 3, 4, 5 and 6.

2 doesn't work. I got confused. 

[Eb7+9]

To be honest I'm trying to ruffle any feathers. I'd really like to hear a short explanation about getting around the idea of having to use matching FETs for things like Phase 45. Which is what I thought Eb+7 was getting at.

Here's the appnote JC was talking about, or I presume it's this one anyway.

http://www.alldatasheet.net/datasheet-pdf/pdf/161774/VISHAY/AN105.html

I've only read it once, so it hasn't all sunk in yet I get the bit about the resistors reducing distortion. but I don't yet see how the information relates to the need or otherwise to match FETs.

that's the one ... ok, let's spill the beans with Ann Margret thrown in for good meaure

aside from distortion issues there are two things to worry about here
they are, the input control range and the output value range

the paper is very clear about defining the input control range,
it is done in terms of the important device parameter Vp ... all the graphs are normalized to that value
the paper assumes "you" know what that value is for your device(s)
it's the starting point of a good design methodology

for example,
fall outside of that range and you hit the asymptotic resistance wall and you'll get "thunk" in the response if there isn't
a limiting resistor in parallel with the jFET channel ... stay within it too much to be safe and not much will happen

also,
have those ranges lay unequal and your devices will not track each other in right proportion - ie., not all your channel
resistances will be moving by same amount cause curve is asymptotic ... in other words you're wasting your time trying to
get something out of your (multi-stage) hardware when some of the stages are just not doing anything ...

why go through the trouble ?

if you're manufacturing units for mass production and yu just want something that "works" that's one thing, but if you're
aiming to DIY a killer phasor me thinks you'd want to use this kind of fuel in your recipe ... otherwise, like Einstein said, you
keep banging your head on the wall and slowly turn insane

---

engineers who are familiar with jFET matching know it's a two dimensional affair as I've pointed out many times ... BJT
devices on the other hand involve estimating Is for matching ... to characterize jFET's one needs to know Idss and Vp
characteristics ... even though there is somewhat of a trend between the two values there also is a random gaussian
distribution offseting the trend ... otherwise, matching jFETs would simply involve resting for one value (may as well make
that Idss cause it's the easiest to measure accurately) ... Vp is not despite what some people think - it's an asymptotically
derived value ...

so, to come back to the above problem one must ask the following question:

does the Keen test say anything about Vp ?
the answer: absolutely not at all ...

otherwise everybody and his favorite pet monkey in industry/academia would already know about it and make use of it
a simple drawing suffices to explain why this is a bogus idea

---

so, enough with that false-matching nonsense ...

let's look at the design of a phasor from a generalized perspective
the same thing applies to opto-cupler based designs btw

you have a resistance range you'd like to control ...
you assume that you have a way of doing the characterization/matching correctly

there are two approaches you can take ...

(i)

one is to take your bag of devices and figure out how to accurately estimate Vp for all of them
(I use an interpolation technique applied to a square-root transformed data set - pretty obvious why)
the result is close to being linear but not quite because jFETs are not perfectly quadratic in transfer
(a moot point really)

after grouping the devices that have close Vp values do an Idss test between them and pair the ones that come out closest
again now, you've got you best shot at having devices that have matching (Vp, Idss) value pairs for a given test voltage

then, from that info, you can tailor a control circuit that will suite the four or six devices you've singled out for this purpose
set the mean value somewhere within the 0v-to-Vp range and make sure the control voltage at the grid stays within that
range then your next and final step is to set the sweep of the voltage so that it lands as close to each end of that range to get
maximal resistance variation from your devices ... if they are properly matched your devices will behave in a similar way within
that range as VCR cells

(ii)

the other approach is to try and fit devices to a given pedal circuit (because it's known to work) - which really, is but a fixed

control circuit ... what you guys are doing is trying to make your device lot fit to the output of that control circuit

take a wild guess which approach has a better chance of landing a more intense sounding phasor circuit ??!

---

this is the same set of constraints I face in my opto-coupler based phasors but in my case I've made it so my control
circuit has an offset and scaling control built in so I can tailor the response to my cells ... so it's very similar except you guys
are forced to deal with a control circuits that generally do not offer those features, plus opto-couplers don't have that
asymptotic resistance wall as jFETs do ...

if it were me and I wanted to get good strong phasing out of jFET's I would first of all select a jFET type that gives me a
comfortable (wide enough but no too wide) control range to begin with - it obviously has to fit within the voltage supply
range for one ... then I would worry about figuring out a better control circuit than what appears in many production line
circuits ... these are often short-cut circuits that won't help you much in this kind of endeavor ...

a simple triangle wave LFO with a variable bias ref and output intensity control should give you the offset and scaling
control you need ... this is all you'll ever really need to know about designing the best jFET phasor possible ...

---

now, the real challenge is figuring out how to estimate Vp more accurately because it can't be measured directly
such an idea as having 3% error at 10nA is complete bologna btw ...


you guys owe me a beer

[jmasciswannabe]

I owe you a couple for the Traynor mods!

[stringsthings]

that's the one ... ok, let's spill the beans with Ann Margret thrown in for good meaure

aside from distortion issues there are two things to worry about here
they are, the input control range and the output value range

the paper is very clear about defining the input control range,
it is done in terms of the important device parameter Vp ... all the graphs are normalized to that value
the paper assumes "you" know what that value is for your device(s)
it's the starting point of a good design methodology

for example,
fall outside of that range and you hit the asymptotic resistance wall and you'll get "thunk" in the response if there isn't
a limiting resistor in parallel with the jFET channel ... stay within it too much to be safe and not much will happen

also,
have those ranges lay unequal and your devices will not track each other in right proportion - ie., not all your channel
resistances will be moving by same amount cause curve is asymptotic ... in other words you're wasting your time trying to
get something out of your (multi-stage) hardware when some of the stages are just not doing anything ...

why go through the trouble ?

if you're manufacturing units for mass production and yu just want something that "works" that's one thing, but if you're
aiming to DIY a killer phasor me thinks you'd want to use this kind of fuel in your recipe ... otherwise, like Einstein said, you
keep banging your head on the wall and slowly turn insane

---

engineers who are familiar with jFET matching know it's a two dimensional affair as I've pointed out many times ... BJT
devices on the other hand involve estimating Is for matching ... to characterize jFET's one needs to know Idss and Vp
characteristics ... even though there is somewhat of a trend between the two values there also is a random gaussian
distribution offseting the trend ... otherwise, matching jFETs would simply involve resting for one value (may as well make
that Idss cause it's the easiest to measure accurately) ... Vp is not despite what some people think - it's an asymptotically
derived value ...

so, to come back to the above problem one must ask the following question:

does the Keen test say anything about Vp ?
the answer: absolutely not at all ...

otherwise everybody and his favorite pet monkey in industry/academia would already know about it and make use of it
a simple drawing suffices to explain why this is a bogus idea

---

so, enough with that false-matching nonsense ...

let's look at the design of a phasor from a generalized perspective
the same thing applies to opto-cupler based designs btw

you have a resistance range you'd like to control ...
you assume that you have a way of doing the characterization/matching correctly

there are two approaches you can take ...

(i)

one is to take your bag of devices and figure out how to accurately estimate Vp for all of them
(I use an interpolation technique applied to a square-root transformed data set - pretty obvious why)
the result is close to being linear but not quite because jFETs are not perfectly quadratic in transfer
(a moot point really)

after grouping the devices that have close Vp values do an Idss test between them and pair the ones that come out closest
again now, you've got you best shot at having devices that have matching (Vp, Idss) value pairs for a given test voltage

then, from that info, you can tailor a control circuit that will suite the four or six devices you've singled out for this purpose
set the mean value somewhere within the 0v-to-Vp range and make sure the control voltage at the grid stays within that
range then your next and final step is to set the sweep of the voltage so that it lands as close to each end of that range to get
maximal resistance variation from your devices ... if they are properly matched your devices will behave in a similar way within
that range as VCR cells

(ii)

the other approach is to try and fit devices to a given pedal circuit (because it's known to work) - which really, is but a fixed

control circuit ... what you guys are doing is trying to make your device lot fit to the output of that control circuit

take a wild guess which approach has a better chance of landing a more intense sounding phasor circuit ??!

---

this is the same set of constraints I face in my opto-coupler based phasors but in my case I've made it so my control
circuit has an offset and scaling control built in so I can tailor the response to my cells ... so it's very similar except you guys
are forced to deal with a control circuits that generally do not offer those features, plus opto-couplers don't have that
asymptotic resistance wall as jFETs do ...

if it were me and I wanted to get good strong phasing out of jFET's I would first of all select a jFET type that gives me a
comfortable (wide enough but no too wide) control range to begin with - it obviously has to fit within the voltage supply
range for one ... then I would worry about figuring out a better control circuit than what appears in many production line
circuits ... these are often short-cut circuits that won't help you much in this kind of endeavor ...

a simple triangle wave LFO with a variable bias ref and output intensity control should give you the offset and scaling
control you need ... this is all you'll ever really need to know about designing the best jFET phasor possible ...

---

now, the real challenge is figuring out how to estimate Vp more accurately because it can't be measured directly
such an idea as having 3% error at 10nA is complete bologna btw ...


you guys owe me a beer

did you get up on the wrong side of the bed today?

[panterafanatic]

I've got this about halfbreadboarded atm, but I'm wondering, what would it sound like (tonally) if you paralleled a stage or two? Would it sound the same or mess with the phasing more. My breadboard is the very small one from Futurlec and I don't think I could fit another IC, hell, I don't know how I'm fitting the FETs on it yet.

[frequencycentral]

After much deliberation of where to take this next, I've decided on a 14 stage implementation. This is based on using four TL084, one for the input stage, one for the LFO and 14 phase stages. This will fit comfortably on a 30x28 piece of perf. I've been having a lot fun with different regen taps, which I'm finding a lot more interesting than switching the number of phase stages. I've also aquired a very small 1P6T rotary switch (thanks!), so have come up with a novel way of gettting a possible 12 different regen types out of one 1P6T switch and one SPDT. By using the SPDT as a 'parity' switch I can select between either odd or even stages, then the 1P6T rotary can select between any of the six odd or six even stages. I've tweaked a few values in the LFO to control the sweep and get the best out of it, and I've completed drawing up the perf layout. Just a few more tests to run..........

I realised this schematic is hard to read, so here's a direct link too: http://dl.dropbox.com/u/967492/Sonic%20Death%20Ray%2014.GIF

[slacker]

Swwwwoooooooosssshhhh 

[frequencycentral]

Swwwwoooooooosssshhhh  

Oh    I was hoping for Swwwwwwwwwoooooooooooooooooooosssssssssssssssssshhhhhhhhhhhhhhh!

Here's the unverified artwork for the 14 stage derivative, quite a few jumpers in the interest of keeping it compact. Not a bad size for a 14 stage phaser! I developed this layout from a 6 stage layout I did, I'll post up the 6 stage too if anyone's interested.

[doc_drop]

O.K. Capt. Perf-ulous,

I'm interested in this again...

If we can't have a sound clip, can you verbally compare the sound to any other "Causalities" we may have heard

[frequencycentral]

If we can't have a sound clip, can you verbally compare the sound to any other "Causalities" we may have heard

Swwwwwwwwwoooooooooooooooooooosssssssssssssssssshhhhhhhhhhhhhhh!