PT2399 mods? What do some of the components do?

[Earthscum]

So, basically I've been playing around with my 2399 for a couple months, but I still haven't figured things out.

I understand how BBD and tape delays work, and digital delays. My question is, what can you do with the external components to 'mod' this chip?

For instance: The caps hooked up to the "MOD" and "DEMOD" modules (pins 7 & . What are their function, and can increasing or decreasing them do anything useful, or balance other modifications?

The input and output filters: can you just use the LPF's as unity gain buffers and use external filters pre and post? I see you should, at least on the output, use about any filter topology you want. If you added external OPAmps for steeper filtering with the internal amps, would it be better to use a fet input TL0xx, or tranny input, or would it matter?

OP1 & 2 (pins 9-12). I see people using different caps here. Stock calls for .1 in the "surround/delay", but .082 for the "echo" application. What do these do? All I can really get is something to do with bandwidth. Are these just for filtering aliasing out of the output signal? If I'm using bass guitar, could I bump these up to something like .22 (half frequency) for some super-filtering for loooong delay times? (did I just figure this out while I typed by chance?)

I'm not gonna even ask about pins 1-6. It's either obvious, or plenty of topics on them.

Thanks a bunch, if anyone has any answers 

Oh yeah, anyone figure out what the longest delay you can squeeze out of this thing before it glitches is? I came across a thread somewhere about the minimum safest delay time (or pin resistance to ground, maybe?) but I can't find anything even closely linked to it now. Read one thread about getting 4 seconds (!!!), but then the chip would shut down for a couple minutes. I figure I'll use no more than half a second or so, but it would be good info to have, since we know the max clock speed.

[frequencycentral]

......and what's pin 5 do: CLK_O

Clock Out? Clock Oscillator? Clock Off? Does CLK even mean clock? Surely it must? Has anyone ever used or experimented with the mystery of pin 5?

[igerup]

As for increasing the max delay time, connect a 100k - 200k linear pot between pin 6 and ground. I did that to my Danaelectro FAB Echo (uses the same chip) and  it opens up someinteresting possibilites. Turned all the way up, the delayed signal becomes really distorted, so I'd recommend a 100k pot. I'm using a 200k myslef. Never turn it up more than halfway (100k ohms, I guess it is) & it gives me almost a 1 sexond delay.  If you want really looooong delays with this chip, I'd recommend using 2 or 4 in the same circuit. There's a few posts made recently about that.

Damn wine messing upmy spelling.  

Pin 5? Is that even supposed to be connected to anything? Not if we look at the rebote scheme. Or in fact any other scheme.

[frequencycentral]

Pin 5? Is that even supposed to be connected to anything? Not if we look at the rebote scheme. Or in fact any other scheme.

But it has a name, CLK_O, it must serve some function. Maybe the device that utilises pin 5 hasn't been made.........yet?  

[igerup]

You have a point there. It could be an internal function thingy, but then the data sheet should say that. Usually CLK is an abbreviation of clock in these matters. And O is obviously oscillator. I honestly think someone should send an enquiring email to the designers/manufacturers of the chip and ask.

[anchovie]

Pin 5 is Clock Out. If you search this forum, you should find a thread where someone ran it through some CMOS dividers to make an LED blink to indicate delay time.

Edit: here it is: http://www.diystompboxes.com/smfforum/index.php?topic=50185.0
Unfortunately the links to the schems don't seem to work any more.

[Taylor]

I've wondered about the mod/demod pins as well.

This chip is fairly mysterious; they don't even explain how the time pin really works, but it seems possible not just to use a varying resistance but also a voltage as in the Magnus Modulus. There is a simple datasheet, the one usually found, and then a deeper datasheet with real internal block diagram, and more information. But even the deep one does not explain the mod/demod. I'd be really interested to hear any ideas anyone has about this.

Edit: somebody suggested that the mod/demod was for external caps in the the ADC and DAC filtering. That doesn't make too much sense to me since the pins are called current control, but it's an idea.

[Earthscum]

I guess I've always assumed pin 5 is "Clock Output". I'm wondering if anyone has it boarded up before I get to it, if they could measure for frequency, and current? One other thread says they measured only mV change. I haven't come across any where someone has measured anything else. Possibly you hook CLK_O directly to the pin 6 on the next chip in a delay chain, so you have 1 pot that controls delay value for all delays after.

That would make sense to me... but what is the controlling factor, and can we utilize it for other purposes? If it's current based, I can think of a bunch of goofy (probably not useful) stuff to do. If it's frequency, the same stuff can be done by using a PWM and an averaging circuit.

[JKowalski]

The time controlling pin I believe attempts to keep a constant voltage on the pin by sourcing current to the resistor. The current needed to maintain that voltage determines the clock frequency. I feel like this was gone over once before and this was what was figured out, but don't completely trust me on that one.

Keep in mind Taylor that it ends up with current - so if you are using current as a control, and you adjust the value of voltage on the other side of the resistor, then the current will change since the voltage across the resistor is diminished. Say 5 volts on one side and typically ground on the other, if you put 1V on the other side instead of ground then the current will diminish. So you can adjust the resistance or use voltage.

CLK_O is clock out, and just gives you a clock output at the frequency of the chip. This is not terribly useful, but if you have another chip that you want and can have synchronized with the PT2399, then this pin can be used to get around having two clock sources on a single board at different frequencies. The fact that it changes depending on delay time may render it useless for most cases but perhaps they figured someone could do something with it?

By the way there are two datasheets, one has more information including a block diagram that lays it out pretty well:

http://www.spelektroniikka.fi/kuvat/2399.PDF

If you look at this sheet you will see that the OP pins are actually integrated op amps in the chip. The intention seems to be to use these for filtering out distortion or clock noise from the digital processing.

Long delay times are not really possible since the memory is limited, and drawing the delay out to 2 seconds or something forces the chip to record with horrible sampling rates. I think there is another chip in the line that allows external memory to be added, but that is not current controlled like this one, only digitally controlled to 16 or so preset delay times.

I guess I've always assumed pin 5 is "Clock Output". I'm wondering if anyone has it boarded up before I get to it, if they could measure for frequency, and current? One other thread says they measured only mV change. I haven't come across any where someone has measured anything else. Possibly you hook CLK_O directly to the pin 6 on the next chip in a delay chain, so you have 1 pot that controls delay value for all delays after.

That would make sense to me... but what is the controlling factor, and can we utilize it for other purposes? If it's current based, I can think of a bunch of goofy (probably not useful) stuff to do. If it's frequency, the same stuff can be done by using a PWM and an averaging circuit.

It may be a open collector buffered output or something similar that needs a pull up resistor to operate...? I think maybe that another person checking out the clock output will see a normal clock signal because that sounds unlikely.  

You cannot hook it up to the pin 6 because that is not direct frequency control as I said but most likely current controlled. Hooking a clock signal to that (and people have tried) does not bypass the VCO. This pin has been heavily looked into in the interests of a simple tap tempo PT2399 delay, and the end result is no, you cannot do it. You need complex external circuitry to control this pin to exact times.

[Earthscum]

Well, if it's clock frequency out, you should be able to do a frequency to voltage conversion (PWM) to extract an envelope to a jfet used as a voltage controlled resistor. Yes, I know... easier said than done, I suppose, considering the speeds involved.

Oh yeah... the LPF Filter amps... are they independent of everything (except signal input to the ADC)? Basically, can you use them as regular OP Amps and use filters other than the MFB filters they show in the app notes? I assume they are from the block diagram, but that may be a bad assumption to make.

For example, can I use LPF2 as a pre filter to LPF1, and implement an external active filter into the output as part of the signal mixing?

[slacker]

Yes as far as I know LPF2 is just an opamp and you can use it how you like. LPF1 works fine if you just wire it up as an inverting gain stage, you don't have to wire it up as shown in the appnotes. Taking the output from pin 12 to external filters should also work fine.

[cathexis]

Pin 5 is Clock Out. If you search this forum, you should find a thread where someone ran it through some CMOS dividers to make an LED blink to indicate delay time.

Edit: here it is: http://www.diystompboxes.com/smfforum/index.php?topic=50185.0
Unfortunately the links to the schems don't seem to work any more.

Here's my vero layout:
http://www.aronnelson.com/gallery/main.php/v/cathexis/Veroboard+Layouts/Magnus+Modulus/PT2399+Tempo+Indicator.jpg.html
Works well, but introduces some noise IIRC.
LARS

[cpm]

"CLOCK OUT" is a clock output for external usage.
you can see it with an oscilloscope

yo can buffer and use for whatever you imagination can think of: divide and count, drive switched capacitors filters, etc

You can easily synchonize two or more chips at the same delay times.
Since the time pin is current driven, use curent mirrors to drive slave chips.
I've used succesfully a mosfet current mirror. I dont know the precission of this methos but as a whole the chips gets the delay time set accordingly with the variations on the master PT.

I have a delay with this implementation, with a posted schematic at ...

as for the maximum delay time... i've achieved, with 2 PT, clean 500~600ms, and noisy-but-usable 1000~1500ms
It's all about the filtering, more filtering means less noise but also a darker sound, you must find a suitable balance.

[Strategy]

I am just getting a Magnus Modulus fixed up for my girlfriend and then I'll be building one. I am loving the way it sounds, my first PT2399 build

is it possible just to inject a CV input in parallel with the LFO's voltage path? Or would it be best to use a vactrol? Has anyone tried alternate control voltage sources with this project? I don't feel I'm enough of a modification ninja to just start hacking this without causing traumatic injuries to the circuit

Advice hugely appreciated...

- Strategy

[Earthscum]

So I guess I gotta ask this, since I don't have a scope to check...

Is the modulated clock signal still at the output, or does this have pre-filtering inside? Reason I'm asking is for the possibility of using the CLK signal to drive a circuit to mix  before filtering to the output or feedback loop. Basically, like your suggestion of using the CLK, and dividing it down to create a digitally modified audio signal echo.

Not sure if it'd work as neat as I like, then again I hardly know what I'm talking about.

[Mugshot]

subscribed! i have a bunch of PTs so might as well learn something new! 

[Earthscum]

I was just looking at (and admiring the simplicity of) Rick's "Little Angel" and looking at the datasheet... and something hit me. Then hit me again. Maybe I just ran into a wall...

Pin 4 is Digital Ground. I was wondering if someone would wanna risk destruction and move that ground up closer to reference? I'm thinking that if you move the DG, it may enable the entire digital system to overclock, critically the osciillator. That would shorten delay times... may also shorten the chip's life, tho.

Maybe someone knows about this already and a chip's life may be spared.  

[earthtonesaudio]

Earthscum asked me to re-post some stuff I wrote in the Little Angel thread.  This post was in response to a question about what OP1/2 and MOD/DEM are used for.  This is mostly guesswork and speculation, but to me this explanation is the only one that fits.

I would say it's mostly about delta modulation, but there's some other fun stuff going on too.


The input signal goes through LPF1 and into the inverting comparator input and is converted to a 1-bit data stream.  This data then goes into OP1 through the box labeled "MOD" in the datasheet.  With the external capacitor, OP1 inverts and integrates this data and is fed back into the non-inverting input of the comparator, closing the loop of the delta modulator.  With too small of a cap, the differential signal at the comparator is very small, so it has a hard time saying whether the input signal is higher or lower than the reference, and the result is drastically reduced gain, except at very high slew rates, where the too-small cap is just barely sufficient to let some signal through.

Because this integrator is part of an overall negative feedback loop, making its capacitor larger reduces the integrator's gain (starting at high frequencies) but increases the gain of the A-D stage as a whole.


Finally, another area of interest is the "MOD" section, which I believe to be a SPDT switch.  The pole connects to pin 8 and so the circuit becomes a switched-capacitor resistor of approximate value R=1/(fC), where f is the clock frequency and C is the capacitor from pin 8 to ground.  So when the clock frequency decreases, the resistor going into the integrator increases, and the integrator's cutoff frequency decreases.  Again, because this occurs in a negative feedback loop, the overall effect is the opposite, such that a decreased clock frequency results in pre-emphasis of treble at the A-D stage.  Meanwhile, the output after the delay goes into OP2, which is similarly modulated by the clock, but here the decrease in clock frequency causes a treble cut, which helps you get away with lower fidelity at longer delay times.