I've been looking through the earlier part of this thread, in particular the behaviour of the VCO when trying to achieve high clock rates. Thomeeque gave these measurements showing that for small CVs and delays, the linearity between CV and BBD delay is lost. This can be seen as a flattening of the straight lines at the far left. I think I can explain what causes this.
I set the CV to a few volts, and used a scope to measure how the clock capacitor voltage changes while charging. The graph of capacitor voltage versus time sort of has two sections. A short section at the very start of the charge process where the cap is being charged at high rate, and a much longer section for the rest of the charge process where it is being charged at a slower rate.
Low CV thresholds correspond to stopping the charge process in the first section where the charge rate is fast, and this gives the flattened CV to delay characteristic on the left of the above picture. Higher CV thresholds correspond to stopping the charge process in the second section where the charge rate is lower and governed purely by the transistor current source. So what causes the high initial charge rate?
I believe the rapid initial charging is due to the reverse current through the discharge diode D2 as it switches itself off. As D2 goes into reverse bias, it takes time for the diode to remove charge carriers and create the depletion region and the associated reverse current through D2 charges up the clock cap. Simulation seems to back this up. There are a few ways of mitigating the effect of this reverse diode current:
1) Increase the supply voltage. Scaling up voltages and currents everywhere makes the effect of diode reverse current less noticeable overall. Decreasing the supply voltage makes the non-linearity more noticeable.
2) Increase the value of the pullup resistor R34 at the comparator output. This makes the diode dump its charge onto the capacitor over a longer time period. The gradients of the two charge sections mentioned above then become more closely matched, but the "knee" between them moves to a higher voltage. Its just a guess, but maybe this explains why the original 9V EM uses a larger pullup resistor than the 15V Deluxe EM (10k rather than 3k3). Unfortunately, increasing R34 makes it harder to drive the 4013 quickly.
3) Use a bigger clock capacitor. This makes the unwanted charge from D2 produces a smaller voltage increase on the cap. This is evident in the graphs above. The curves flatten out at lower CVs as the clock cap increases in value. Note that changing the charge current using the trim pot RT3 only changes the gradient of the large linear portion of the graph. There is little effect on the location of the "knee" i.e. the voltage at which the curve flattens out.
4) Keep the CV away from the non-linear region. In other words, work out the limitations of the VCO and design an LFO section to match it.
It's interesting that the type of measures taken to speed up the VCO cause the non-linearity to get worse. e.g. lowering the pullup resistor or using a smaller clock cap.
Although the EM3207 schematic shows a 22pF timing cap, Thomeeque later recommended 47pF on this thread and I would agree based on the above graphs and explanation. It is better to use 47pF and higher charging current (by adjusting clock trimmer) than to use 22pF and lower charging current. Funnily enough, the Madbean Current Lover and Hartmann Flanger (both clones of the 9V EM) use a 22pF timing cap rather than 47pF. So you can probably just about get away with 22pF so long as the CV doesn't reach the non-linear bit of the charging curve.
So why not use an even bigger cap and charging current? I think there is a limit as to how big you can make them. If you scale both up by a factor of 10, then the capacitor will have to discharge 10 times as much charge, and this becomes harder to do because the comparator realises the cap voltage has dropped and shuts off the diode before the capacitor can "fully" discharge. (Note that the capacitor never fully discharges anyway because of the voltage drop across D2).
I see there is a design earlier in this thread for a faster VCO which claims to match the aim of doubling the Deluxe EM clock rate while keeping a linear characteristic.
Has anyone (other than the designer) built and tested the VCO in the following link ... ?http://www.diystompboxes.com/smfforum/index.php?topic=91981.msg803653#msg803653 It uses 22pF and a low value pull-up resistor. So the nonlinearity in the CV to delay characteristic should be worse, but the CV appears to be kept deliberately high (1.6V to 6V) so I am thinking it stays away from the non-linear part of the characteristic.
I'm asking 'cos I'm toying with the idea of a Deluxe EM clone using the 3207 but running on 9V instead of 15V.
