For the curious, that's done with R16. You can safely do this to any RAT to help with JFET cutoff due to signal level, but it won't magically make any JFET work.
The main use of the gate bias trick is to help bias low VP JFETs when they replace higher VP JFETs. You can use the biasing method for any JFET but for 9V circuits it might turn out better not messing with the gate voltage.
For a buffer circuit the source voltage can limit the swing. The gate-source voltage swing is quite low for a buffer, even when the swing on the gate is large, because of the natural negative feedback.
With the bias arrangement of the turbo rat, you can use your j201 without a problem. You could in that case decrease the source resistor to 4.7k to boost the current a bit.
For a J201 Turbo RT I'd keep the source resistor at 10k. With a lower source resistor Id_pk = (Vo_pk + VS_bias)/RD can exceed IDSS for the J201 on the positive swing.
To maximize swing you would bias the source so it is close to cutting out on the *largest* negative swing, and just hitting IDSS on the largest positive swing. With a circuit like the RAT with limit input range you don't *have to* go that far but you at least have to be sure it's not going to bottom out on the -ve swing (Vs=0, Id=0) or hit IDSS on the positive swing.
Using the National Semiconductor J201 model, and tuning the gate bias voltage, roughly,
- For Rs = 10k the maximum input swing is +/-3V when the source is biased to 3.0V.
- For Rs = 4k7 the maximum input swing is +/-1.5V when the source is biased at 1.4V to 1.5V
In both cases (Vo_pk + VS_bias)/RD hit IDSS but the Rs=10k case does it at a higher swing.