BBD Clock - MN3102 ?

[tss]

I just got the Cool Audio clone of the MN3102 (V3102). The datasheet is minimal, however I think I hooked up everything correctly. The positive supply is 5V. I hooked up a 10K resistor and a 22pF cap so the freq. is around 600KHz. I connected two scope probes to the CP1 & CP2 outputs and this is what I saw:


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I never worked with these devices in the past, so I have two questions:
1. Is this a normal waveform for this IC? It seems like a pretty poor clock to me. Is it "squarish" enough?
2. There are two outputs, is this how they should appear?

[Mark Hammer]

The clock output is affected by the input cpacitance of whatever it is feeding.  The datasheets for the MN3102 spec it up to 100khz or so, because the devices it would normally be used with, like the MN3207 or 3205 or 3204, had sufficient input capacitance on the clock pins that the pulse would be decidedly less squarish at frequecies above that.

It can be helped along by buffering the 3102 output and providing more current drive.

[tss]

The clock output is affected by the input cpacitance of whatever it is feeding.  The datasheets for the MN3102 spec it up to 100khz or so, because the devices it would normally be used with, like the MN3207 or 3205 or 3204, had sufficient input capacitance on the clock pins that the pulse would be decidedly less squarish at frequecies above that.

It can be helped along by buffering the 3102 output and providing more current drive.

Yes, that makes sense! The capacitance of my scope probes is marked 90pF (actual is over 100pF @ 1KHz and who knows at 600KHz). The input capacitance of the clock PIN on the MN3205 (similar to what I'm using - V3205 by Cool Audio) is 2800pF max. I'll have to look at that signal once I'll hook up the BBD. Going to look like a trapezoid!

[tss]

OK so I lowered the clock speed and now the clock looks much much nicer!
I hooked up a Cool Audio V3205V to the clock signals and various supplies. I am wondering, what would be the most simple test circuit for this? I could not figure out what output is expected at the two outputs (why there are two?). Currently they output a DC voltage. Another question, can I simply input, say, a 1Vppk 1KHz signal biased to 0.5Vdc and expect to see a delayed signal? This far it did not work very well... I made sure the input is indeed as I wrote it (after adjust a signal source that is optimized for a 50 Ohm load).

[gena_p1]

it is is normal
for example mn3102 diagrams: http://forum.gtlab.net/cgi-bin/yabb2/YaBB.pl?num=1253074266/260
all as described in datasheets