Quote from: dschwartz on November 22, 2018, 01:07:11 PM
I'm reading the article, i love your analysis !
Just point out that the opamp stage is non inverting, though.

Well spotted! Thanks.

If you see anything else...

T.

Quote from: ElectricDruid on November 22, 2018, 01:46:13 PM

Quote from: dschwartz on November 22, 2018, 01:07:11 PM
I'm reading the article, i love your analysis !
Just point out that the opamp stage is non inverting, though.

Well spotted! Thanks.

If you see anything else...

T.

Well..on the OD section, you mention that the clipping is "softened" by the series 10k before the shunt clipping dioded.. i think 10k will make the diodes clip pretty hard. Lower resistance makes the shunt clipping softer.

On the first page of the factory schematic, the H1A and H1E designations are reversed. H1A is the signal input and H1E is the power input.

Also, on the last page, it seems to indicate that the H1A (signal) connects to the electronic bypass switch control. I suspect that is incorrect and the bypass designation should be H1D on the last page.

Finally, isn't the input signal always mixed into the output via R74? The DC through this resistor from U1A also provides the bias for the output buffer.

If H1D is the bypass, since it blocks the parametric output from going into the buffer, then what turns the Overdrive channel On/Off?  Q10 and Q11 are active at the same time and serve to isolate the Metal channel from going to the parametric. How is the Overdrive channel disabled? Or is it always going to the output (in parallel with the Metal channel) when the effect is enabled?

U3A and U3D seem to be serving the dual purpose of enabling the parametric and driving the channel indicators and switches.

I think the DIP switch SW3C disables the parametric at all times and not just for the Metal channel. (The para never seems to be engaged for the Metal channel, even with SW3C open, since the channel selector is driving it)  Perhaps a more detailed look at the switching would be beneficial.

Given that there seem to be some errors in the factory schematic, I could be way off here! 

Best regards, Jack

Quote from: dschwartz on November 23, 2018, 07:26:51 AM
Well..on the OD section, you mention that the clipping is "softened" by the series 10k before the shunt clipping dioded.. i think 10k will make the diodes clip pretty hard. Lower resistance makes the shunt clipping softer.

Thank you, you're quite right. I was remembering it the other way around, but it's not like that. I'll correct it.

This is *exactly* why it's important to get some other sets of eyes to have a look at something...

It's much appreciated and makes for better work. Thank you.

T.

Quote from: amz-fx on November 23, 2018, 09:35:49 AM
On the first page of the factory schematic, the H1A and H1E designations are reversed. H1A is the signal input and H1E is the power input.

Also, on the last page, it seems to indicate that the H1A (signal) connects to the electronic bypass switch control. I suspect that is incorrect and the bypass designation should be H1D on the last page.

Yes, I'd also spotted this. The "connections" between the "Jacks and switches" schematic sheet and the two pages of the main schematic don't seem to line up much at all!

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Finally, isn't the input signal always mixed into the output via R74? The DC through this resistor from U1A also provides the bias for the output buffer.

Yes, I thought so. There's always a path from the input to the output. The FET switches only take the other signals out. It must be a nightmare to have anything like reasonable levels between the "bypassed" and "effect on" signals.
I've not dealt with any of the switching in my article. It just seemed like a whole other can of worms to open, so I just avoided it. I realise that means there's quite a bit left out. QUITE a bit. Another day, perhaps.

But I should mention just how much there is that I've not mentioned, if you see what I mean. The article comes across as pretty complete, and in fact, it's only really a first try. And the routing craziness is a big part of that.

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If H1D is the bypass, since it blocks the parametric output from going into the buffer, then what turns the Overdrive channel On/Off?  Q10 and Q11 are active at the same time and serve to isolate the Metal channel from going to the parametric. How is the Overdrive channel disabled? Or is it always going to the output (in parallel with the Metal channel) when the effect is enabled?

I think it is always enabled. This is another bizarre design decision in this pedal. By the time I got to this point, I wasn't even surprised any more. It's weird, but that seems to be what it does. The only FET switch between output of the overdrive stage and the output buffer is after the parametric EQ, which I assumed is to turn the whole effect off. To me that means there is no way to turn the overdrive stage off.

It seems we've always got clean signal, and we can then add the effect signal, and that effect signal is either just the Overdrive channel, or both the Overdrive channel and the Metal channel mixed together.
It's a truly odd pedal when you get into it. That's why I find this stuff so fascinating. I'm really struggling to reconstruct the thought process that made people think that was a good idea!! I suppose you'd have to mod it to separate out the parts and then you could see. Perhaps it sound hopeless with each bit on it's own!

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U3A and U3D seem to be serving the dual purpose of enabling the parametric and driving the channel indicators and switches.

Agreed, they do.

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I think the DIP switch SW3C disables the parametric at all times and not just for the Metal channel. (The para never seems to be engaged for the Metal channel, even with SW3C open, since the channel selector is driving it)  Perhaps a more detailed look at the switching would be beneficial.

Hoho, yes, "a more detailed look would be beneficial". For me, that's a technical way of saying this part confused the hell out of me!
I thought perhaps the DIP switch only disabled the parametric when the channel selector driving it was set to the Metal channel, but I haven't worked it through thoroughly.

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Given that there seem to be some errors in the factory schematic, I could be way off here! 

I think you're more right than they are, Jack, TBH...

Thanks,
Tom