One last suggestion..

Either move D3 Cathode to +9V or make V3 +9.55V unless you intentionally aim to reduced headroom..

C2 is polarity backwards, even though it's only 100nF, a usually non-polar size for caps.

QuoteSo far, I only know of STEP command to be able to get a retrace of same data (but with different parameters). But I could not see a STEP command in the graphic

Feature to compare last waveform to current waveform would be great. How does that one work ?

For time between Data, I like to begin with 100 data points per cycle as the minimum, and sometimes going up much higher.

I only use STEP but I thought there was a way to load in results of other simulations.   I can't actually see how to do it  .

In the past I've seen spice produce incorrect simulations when the step size is too large.  Imagine a 1MHz waveform feeding a circuit for 1s stepped at 0.1 sec.   The errors are more than undersampling the 1MHz waveform at 0.1sec the solver gets lost numerically by solving the differential equations with large steps.

I think the step we specify in transient analysis is the Max step

And spice uses some min step by using its own brains.

QuoteI think the step we specify in transient analysis is the Max step

And spice uses some min step by using its own brains.

Spice tries to automatically determine the step size but it judges its success based on some convergence criteria.   What can happen is it jumps too far ahead but numerically it still see the solution converging at that distant point.   The initial step might have skipped a lot of history require to converge at the *correct* solution.   Imagine a step waveform going into a circuit which has a 10ns rise time.   If the effect of the rise-time affects something important in the simulation the automated stepping could jump 1us and completely miss the 10ns feature.    For example a circuit which measures the signal slope by differentiating the signal and feeding it into a peak detector.    All automated numerical processes on a computer fail at some point.   If you want to guarantee a good solution really need to force the steps to at least represent the known features of the waveforms in the circuit, that might mean the steps need to be somewhere in the 1ns to 5ns region.    The downside is if there are large regions of time where the circuit is doing nothing the simulation will be slowed down by the smaller steps.  Nonetheless there's no point having quick simulations with wrong answers.

In AI you have a similar issues when selecting the learning rates.   For finite element simulations you have similar problems with the mesh size.

Quote from: antonis on November 15, 2021, 05:03:54 AM

Quote from: YurkshireLad on November 14, 2021, 06:47:40 PM
I haven't modified any values yet, but this is what I have so far.

No need for 3 X 1M bias configuration resistors..
(make R7 & R8 10k to 47k, say..)

If I take out R1, then (as pointed out by a couple of people here) the signal bleeds to ground through C6?

Quote from: antonis on November 15, 2021, 08:18:16 AM
One last suggestion..

Either move D3 Cathode to +9V or make V3 +9.55V unless you intentionally aim to reduced headroom..

Interesting; I borrowed the power circuit from the Boss DS-1. Perhaps the DS-1 does something special to compensate for this?

Quote from: duck_arse on November 15, 2021, 08:26:15 AM
C2 is polarity backwards, even though it's only 100nF, a usually non-polar size for caps.

I used to have it reversed, but someone suggested I reverse it to what I have now. 

Thanks all - awesome help, which is much appreciated. Even if I don't always understand what you're talking about! 

Quote from: YurkshireLad on November 15, 2021, 10:53:23 AM

Quote from: antonis on November 15, 2021, 05:03:54 AM

Quote from: YurkshireLad on November 14, 2021, 06:47:40 PM
I haven't modified any values yet, but this is what I have so far.

No need for 3 X 1M bias configuration resistors..
(make R7 & R8 10k to 47k, say..)

If I take out R1, then (as pointed out by a couple of people here) the signal bleeds to ground through C6?

Antonis meant

Keep R1 as 1 Megs

Reduce R7 and R8 to something between 10 k to 47 k each

Quote from: Vivek on November 15, 2021, 11:10:48 AM

Quote from: YurkshireLad on November 15, 2021, 10:53:23 AM

Quote from: antonis on November 15, 2021, 05:03:54 AM

Quote from: YurkshireLad on November 14, 2021, 06:47:40 PM
I haven't modified any values yet, but this is what I have so far.

No need for 3 X 1M bias configuration resistors..
(make R7 & R8 10k to 47k, say..)

If I take out R1, then (as pointed out by a couple of people here) the signal bleeds to ground through C6?

Antonis meant

Keep R1 as 1 Megs

Reduce R7 and R8 to something between 10 k to 47 k each

Ahhhhh! My apologies Antonis! 

I'm not getting a double signal on the output, so I probably made a stupid mistake in configuring the simulation. Though I'm getting a gain of less than 8 now.

Re. the "Megs" and 10ks...did you go look at the link(s) I posted of other circuits?  Just copy the power filter/bias network!  Distortion plus is good, but as Antonis said, make the 1 megs in the network (R7, R8) 10k, 22k or something like that.   Keep R1, the 1M, to the opamp input.   Done in one.

Don't worry about the ultimate 'performance' at this moment...we need to get your circuit configured well, and your LT running right   Don't forget, it's a sine wave, there is averaging involved (120V house voltage is more like 170 peak)

Thanks. I did look at them, but I just revisited them now that I'm a little bit more comfortable looking at simple (parts of) circuits. The Proco Rat power circuit looks interesting.

Quote from: YurkshireLad on November 15, 2021, 10:54:55 AM

Quote from: antonis on November 15, 2021, 08:18:16 AM
One last suggestion..
Either move D3 Cathode to +9V or make V3 +9.55V unless you intentionally aim to reduced headroom..

Interesting; I borrowed the power circuit from the Boss DS-1. Perhaps the DS-1 does something special to compensate for this?

Hmm, this is the schematic I found - https://www.electrosmash.com/images/tech/ds1/boss-ds1-distortion-schematic-parts.jpg

Which schematic is identical to many other similar power supplies..

That diode is placed between +(9V) and -(GND) and serves as reverse polarity protection diode..
(it shorts the reverse polarity supply..)

Safer for power supply should be a SERIES Schottky diode (right after +9V input) in the cost of 250 - 350 mV drop..

P.S.
Better implement a 1N400X diode (1A) in case of PS shunt diode unless you wish for 1N4148 signal diode to serve as a fuse also..

The diode won't conduct if everything is 'normal'...it is reverse-biased in operation. If the power adapter is plugged in in the right polarity (it's not shown here), and if the battery is connected the right way, it's like it's not there. If either is reversed, the diode shunts the WRONG polarity supply to ground and hopefully protects the semiconductors down the line.   It should be 'beefier', to conduct the reversed current without burning itself out.   1N4148 (1N914) are too low rated to do this for very long!  But we see them in many designs.  They're only good for a quick WOOPS when putting in the battery.

Ignore the diode in your simulations, it's not doing anything in that regard.

The Rat has a neat supply, yes.  Big cap / little cap for noise and reservoir, the low-value R there to work with caps as a filter. A bit 'fancy', but works very well.  I try to keep it simple!  That is the basic idea, the DS-1 or the Rat.   

I stumbled across this video from Wampler of the Rat's circuit, which gives me an excellent explanation of what each component does. Fascinating.

https://m.youtube.com/watch?v=zBGKdnlh4Ws

The interesting thing about this is

When all quirks have been righted

All mistakes corrected

Best practices adopted,


Your circuit will become exactly same as 1000 others

Who started at random designs

And converged to almost same final point.


For example, everyone has voltage divider with 10k, and 1M going to Opamp as Vref.