EM3207 (v1.1) - MN3207 based EHX Electric Mistress (9V) clone

[Eduard_Solderingironhands]

Hello Thomas,

Nice, you are probably first one, how do you like it?

Sorry, but I can't judge yet. I haven't played it much. I soldered it together, looked if it is working and measured the LFO and VCO. I didn't even adjust all trimm pots by now.

The Resissue is 1.4 V to 8.0 V @ 12 V, which equals 12 % to 67 % - in Flange mode.

My colleague guessed the oscillation comes from the 1N4148. He suggested to put a small capacitor from the output of the LM319 to GND to slow down the LM319 a bit. A already tried this but the capacitor makes the limit of the 4013 slower. But as the 4013 is too slow anyway I will try this next:

A 74AC74 instead of the 4013. The problem is that the 74AC74 can be only operated at maximum 7 V. We need a resistor as voltage divider parallel to the capacitor. I am not sure if this resistor will cause unexpected problem for the negative input of the LM319. But we will see.

Best wishes

Ralf

[Thomeeque]

The Resissue is 1.4 V to 8.0 V @ 12 V, which equals 12 % to 67 % - in Flange mode.

 Hmm, maybe it's not EC1000 or it does not match 100% with schematic I've got.. nevermind, not important..

My colleague guessed the oscillation comes from the 1N4148. He suggested to put a small capacitor from the output of the LM319 to GND to slow down the LM319 a bit. A already tried this but the capacitor makes the limit of the 4013 slower..

 Did you try smaller value for R34 to make comparator output stronger? With Tesla MAB311 and R34=1k I have got to 3MHz at the 4013 output, so maybe 4013 is not bottleneck here..?

 Btw. I've seen those oscillations when emulating the clock in LTSpice - I thought it was caused by some LTSpice approximation or something similar and now I see that it was correct, interesting!

 And another btw.: that R3/R4 divider as supply source for 74AC74 won't work, it's way too weak source..

 Cheers, T.

[Eduard_Solderingironhands]

Hello Thomas,

reducing R34 to 1k helps to reduce the unwanted oscillations of the LM319 and helps to increase the maximum frequency out of the 4013. With a Schottky diode for D2 instead of the 1N4148 I had 7 MHz at the otuput of the 4013. New speed record

But I could not achieve a lower frequency than 150 kHz. A capacitor between LM319 out and GND doesn't help at all. Changing D2 with different diodes only resulted in higher frequencies, not lower. I am not sure if the LM319 is the right way. I think it is too fast.

Best wishes

Ralf

[Thomeeque]

Hello Thomas,

reducing R34 to 1k helps to reduce the unwanted oscillations of the LM319 and helps to increase the maximum frequency out of the 4013. With a Schottky diode for D2 instead of the 1N4148 I had 7 MHz at the otuput of the 4013. New speed record

But I could not achieve a lower frequency than 150 kHz. A capacitor between LM319 out and GND doesn't help at all. Changing D2 with different diodes only resulted in higher frequencies, not lower. I am not sure if the LM319 is the right way. I think it is too fast.

Best wishes

Ralf

 I've just started my first experiments with LM319 in my clock replica before a while, I've got very high frequencies at 4013 outs too (around 5MHz with 1N4148), I was not sure if it's not just measuring error (I cannot use my pseudo oscilloscope at these frequencies and I'm not sure how much I can rely on my frequency meter either), so I'm really glad for your results - so even 7MHz, wow!

 Comparator should not be "too fast" for this VCO - at least basic principle of this clock - how I understand it - is that constant current source (emitter of Q2) charges C17 until voltage on this capacitor is bigger than control voltage at positive input of comparator, then comparator flops and discharges C17 rapidly via D2, flops back and charging of C17 starts again. Biggest the control voltage is, longer charging takes - so with bigger voltage period grows, frequency decline (and vice versa). It's well visible here. So even infinitely fast comparator should work here, frequency is not set be it's speed (I'm still talking about basic principle - in reality and especially at high frequencies everything metters as we well know already), it's set by current ("clock trimmer" RT3) and by value of the capacitor.

 So, try to increase value of C17 and lower charging current to get frequencies down, it should be the way..

 T.

[Eduard_Solderingironhands]

Hello Thomas,

Increasing C17 or lowering the charging current doesn't help. With lower charging currents the LM319 gets unwanted oscillation.
Increasing C17 only alters the u to f function but not the maximum lowest frequency. The LM319 has almost no hysteresis. If the voltage at V- is greater than V+, the ouput will toggle to low and C17 will be discharged over the comparator. But immediately after the output toggels to low and the discharging starts, V- will drop below V+ and the otuput will toggle back to high before C17 is fully discharged.
That is why we probably need a slower comparator or some kind of hysteresis.
With a fast comparator it may be easier to go to 5.12 MHz to 116 kHz and use the second FilpFlop of the 4013 to devide the frequency into half.

Best wishes

Ralf

[Thomeeque]

 Ralf, you're good! What you say makes perfect sense. I got to admit, that I was little unsure all the time about the phase where the capacitor gets discharged, about what and why happens there exactly, my understanding was too simplified.

 Could we somehow use second half of 319 to slow comparator down?

 Thanks, T.

[Valentinych]

Hi all!  
Friends, you are giving too much emphasis on VCO LM311 … There are more important conditions MN3x07 management. In datasheet on these chips specified Clock Pulse Waveforms CP1 and CP2:

 
                                MN3007                                                                                MN3207

From the datasheet that the clock cross point (Vx) CP1/CP2 MN3007 for should be based not below 3 volts, and 1.7 volts MN3207 not above GND level.

When generating speed through triggers (4013, etc.), the clock cross point has a level 1/2 Vdd means BBD works not in an optimal mode.
A few years ago, I experimented, and compared the treatment of clocking by using MN3102 and 4013. At high frequencies (above ~ 500 kHz) S/N output 3207 in "trigger" mode was markedly worse than in regular mode. In addition, the output level was less than ~1.5-2 dB.  This is because the principle of BBD.

I recently made new measurements of clocks, MN3207 clearly visible delay fronts phased impulses. The delay time is absolutely does not depend on the frequency. Photo taken on my Takwey DST1202.
Vdd = 9V. CP1 showing in yellow, CP2 shown in blue:


Waveforms at 53.29 kHz. Delay front 140 ns.


Waveforms at 172.95 kHz. Delay front 140 ns.


Waveforms at 495.8 kHz. Delay front 140 ns.


Waveforms at 1.805 MHz. Delay front 140 ns.



Waveforms at 53.17 khz. Maximal amplitude of rectangular form.


Waveforms at 318.84 khz. Amplitude and waveform does not change.


Waveforms at 1.015 Mhz. Amplitude and waveform does not change.


Waveforms at 1.62 Mhz. Amplitude and shape of the wave is beginning to change.


Waveforms at 2.01 Mhz. Amplitude and shape wave greatly changed. Clearly expressed asymmetry phases.

As the experiments showed my MN3102 quite satisfactorily generates at frequencies up to 2 Mhz, 4 MHz frequency which corresponds to the comparator LM311. The MN3102 generates the necessary delay fronts. However, since the frequency of ~ 1.2 -1.5 MHz pulse form is not symmetric and strongly CPx tamed, and reminds the bell, rather than a rectangle.
Moreover, at such high frequencies MN3102 cannot provide fast charge input capacitance MN3207, which is used in most development flangers.

But if the output MN3102 to fix an additional buffer (4049) as in the diagram by Thomas from the first message, everything is great!
An even better result would be, if the buffer is 4049, and the special dual high-speed MOSFET driver type MIC4424, or similar.  Such drivers I have few years apply in our developments on BBD.  

Good luck to all! Igor (aka Valentinych).

P.S. Sorry for my bad English ...

[12Bass]

When generating speed through triggers (4013, etc.), the clock cross point has a level 1/2 Vdd means BBD works not in an optimal mode.
A few years ago, I experimented, and compared the treatment of clocking by using MN3102 and 4013. At high frequencies (above ~ 500 kHz) S/N output 3207 in "trigger" mode was markedly worse than in regular mode. In addition, the output level was less than ~1.5-2 dB.  This is because the principle of BBD.

Informative post, Valentinych!

When you mention signal loss as a "principle of BBD", are you saying that BBDs inherently have lower gain at high clock rates?  This is indicated on the datasheets, IIRC.  Does a rounded clock signal impact the gain, or just the fidelity of the signal?

Would you happen to have any clock waveform traces with a 4049 buffer in place?  I've built an A/DA flanger clone using an SAD1024A with a 4049 buffer in the clock circuit.  It is calibrated for up to 2.6 MHz at the very top (0.2 mS).  From what I understand, the Reticon BBDs have less capacitance at the clock inputs and thus do not round off the clock signal as much as the Panasonic MN devices.  Still, I'd be curious to see what the clock waveform looked like with and without the 4049 buffer in place.

[Valentinych]

When you mention signal loss as a "principle of BBD", are you saying that BBDs inherently have lower gain at high clock rates?  This is indicated on the datasheets, IIRC.  Does a rounded clock signal impact the gain, or just the fidelity of the signal?

OK. I'll try to prepare a response, and will write later.

[Valentinych]

Principle of operation BBD is based on moving electric charge consistently from one potential holes in another.
The entire line is split into odd and even levels (cells). All even-numbered (and odd-numbered) cells are connected to input controls, and managed at the same time. Therefore, control signal has two phases – CP1 and CP2. 
When the input signal is chip CP1 high-level you record level input LF-signal in the first cell, and simultaneously charge transfer from the second (fourth, sixth, etc.) of the cell in the third (fifth, seventh, etc.). Signal from the last even cells in this time shall be applied to the output circuits. 
When the input signal is CP2 high-level, shifting charges from all odd-numbered cells (third, fifth, etc.) in the following even-numbered cells (the fourth, sixth, and so on). Signal from the latest odd cell at this time is output circuits.
Time CP1+CP2 determines the period of the clock frequency.

But for transfer charge from one cell to another requires some time (Tmin), then the signal duration CPx must be greater than the minimum time Tmin. Therefore, the maximum clock speed control signals are defined as Fclock <= 1/(2 * Tmin). 
For the full transfer charges in real chips still required some time Tdead, which shares the signals CP1 and CP2. It is well visible on my photo above. 
If Fclock will have more maximum, or Tdead less than the required time, happen not full migration charges from cell to cell, or partial mixing charges of adjacent cells. 
These causes reduced signal level output BBD on high Fclock’s, and the deterioration of the signal/noise ratio.

Hopefully, someone will understand what I wrote!   

[12Bass]

Re: BBD operation

If I'm understanding correctly, Igor is saying that past a certain clock rate the BBD cannot effectively transfer a full charge from cell to cell and begins to lose output.   This loss of transfer efficiency would also appear to depend on the relative spacing and shape of the clock pulses.  I wish that I had an oscilloscope so that I could observe the changes in the clock signal as frequency goes up, plus the impact on the audio signal.  Even though this technology is decades old, it is still quite fascinating! 

[Eduard_Solderingironhands]

Hello,

I can confirm the volume loss of the BBD at very high clock frequencies. Today I managed to to get the LFO and VCO to make the MN3207 sweep from 0.2 to 8 ms. Although the MN3207 is working up to 2.56 MHz (0.2 ms delay) there is no effect audible at these short delays.

I decided to quit developing the Mistress and get a used vintage one.

In case anyone wants to continue development and put the mojo in the mistress, here is my new VCO:



Vcrtl_min = 1,60 V, Vcrtl_max = 6.0 V for the new VCO.

For the LFO I changed R22 to 15k + 220, R21 to 10k, and R27 to 100k. The LFO would require a bit more fine tuning.

Best wishes

Ralf

[Thomeeque]

 Interesting posts, guys, thanks Igor for jumping in!

 Ralf, that clock looks impressive! Was is possible to get lower frequencies yet?

 I did measure GAIN/CLOCK characteristic of my unit:

 V_CC = 10VDC
 R34 = 1k
 IC4 = Tesla MAB311
 f_CLOCK = 40kHz ~ 3MHz

 Input = 200Hz / 525Hz / 1.5kHz sinus adjusted for 1V_PP at pin 3 (input) of BBD

 GAIN is ratio between peek-to-peek voltages at R15 and at pin 3 (input) of BBD, measured by Velleman PPS10 oscilloscope.

 FILTER-MATRIX mode, COLOR at 0.

 
 (click pic for hires)

 Results were quite surprising (for me) - characteristic depends on input signal frequency and for some (low) input frequencies gain drop stops around 1400kHz and gain slightly grows again (!!) with higher clock. For higher frequencies drop is continual and signal gets distorted above 2.4MHz (there is maybe space for bias voltage tweaking yet).

 T.

[Valentinych]

Guys, I think we speak, but often do not understand each other.
Let us define some terms to prevent misinterpretation.

Fclock (Fcp) - frequency phased control impulses BBD on the pins 2, 6 of chip MN3207.
To obtain the time delay our BBD (MN3x07) from 16 ms to 0.4 ms this frequency should vary from 32 kHz to 1280 kHz.
Increase Fcp over 1.3-1.5 MHz is meaningless, because a delay of less than 0.3 ms effect does not occur even in filter-matrix mode.

Fvco – the output of the VCO frequency. From Thomas it is pin 7 of chip LM311.
At this point, the frequency shall be two times higher than at the entrances to the CP1 and SP2 MN3207.  Mean Fvco range must be between 64 kHz to 2560 kHz.

Even if a VCO using MN3102, then Fvco will not be equal to Fcp: on pins 5, 6, 7 of MN3102 the frequency is X (Fvco), and the pins 2, 4 of MN3102 the frequency is X/2 (Fcp).

The last graph by Thomas cannot be analysed without considering frequency characteristics throughout the schematic.
The signal is filtered before BBD and after BBD. Likely rise gain at frequencies below 1 kHz depends not on MN3207, but on amplitude-frequency characteristics of the entire tract.

[Eduard_Solderingironhands]

Hello Igor,

If you take a look at page 2 of this thread you will see that Fclock (Fcp) of the vintage EM goes from 1280 kHz to 29 kHZ which equals a delay of 0.2 ms to 8.8 ms by the SAD1024. The very short delay of 0.2 ms is clearly hearable and the difference why the vintage versions sounds different than the new Deluxe or DIY versions.

As the MN3207 has 1024 buckets instead of the 512 of the SAD1024 we need Fclock twice as fast which is 2560 kHZ to 58 ms. Fvco must be evan twice (5120 kHZ to 116 kHz).

Best wishes

Ralf

[Thomeeque]

Guys, I think we speak, but often do not understand each other.
Let us define some terms to prevent misinterpretation.

Fclock (Fcp) - frequency phased control impulses BBD on the pins 2, 6 of chip MN3207.

 Everywhere in this thread where I do mention clock frequency, f_CLOCK, f_c etc., I mean frequency at BBD's clock pins (CP1/CP2 of MN3x07, Φ_1A~2B of SA1024), f_CP.

To obtain the time delay our BBD (MN3x07) from 16 ms to 0.4 ms this frequency should vary from 32 kHz to 1280 kHz.
Increase Fcp over 1.3-1.5 MHz is meaningless, because a delay of less than 0.3 ms effect does not occur even in filter-matrix mode.

 Delay of less than 0.3 ms occures in FLANGE mode of my friend's vintage DEM15 I have measured and recorded. FLANGE mode range is slightly bigger than F-M mode range in case of this unit.

Fvco – the output of the VCO frequency. From Thomas it is pin 7 of chip LM311.
At this point, the frequency shall be two times higher than at the entrances to the CP1 and SP2 MN3207.
Even if a VCO using MN3102, then Fvco will not be equal to Fcp: on pins 5, 6, 7 of MN3102 the frequency is X (Fvco), and the pins 2, 4 of MN3102 the frequency is X/2 (Fcp).

 Yep.

The last graph by Thomas cannot be analysed without considering frequency characteristics throughout the schematic.
The signal is filtered before BBD and after BBD. Likely rise gain at frequencies below 1 kHz depends not on MN3207, but on amplitude-frequency characteristics of the entire tract.

 Filtering before BBD is not relevant, as stated above amplitude at the very input was adjusted to be 1V_PP at the BBD input before each measurement.

 Filtering after BBD (basically only R12-R14 + C17, I did measure "output" voltage at the R15 ~ Q1 buffer output) is not relevant either - first because even at 1.5kHz it has almost no impact on passing signal (C17=680pF @ 1.5kHz ~ 160kΩ) and second because frequency of passing signal remains constant during the measurement, it should not alter shape of the GAIN/CLOCK characteristic (actually, it could alter it as it forms load for BBD outputs, but I believe it's not what you are saying), it would just move it up or down.

 T.

[Thomeeque]

I can confirm the volume loss of the BBD at very high clock frequencies. Today I managed to to get the LFO and VCO to make the MN3207 sweep from 0.2 to 8 ms. Although the MN3207 is working up to 2.56 MHz (0.2 ms delay) there is no effect audible at these short delays.

 Ralf, what BBD chip did you use exactly? MN3207 (Panasonic/Matsushita), BL3207, V3207..?

 Btw. was R2 necessary in your new LM319 VCO?

 Cheers, T.

[Valentinych]

Hi, Ralf!
I agree with what you wrote.
However, if you look in datasheet SAD1024, you can see that this chip is designed to work with frequency up to 1 MHz. 
The manufacturer guarantees the work of MN3207 only up to the frequency of 200 kHz, and MN3007 even less – up to 100 kHz. Increase up to 1.2 Fclock -1.5 MHz to SAD1024 practically does not affect the chip. 
But to get the same delay will increase MN3207/3007 Fclock in 25/50 (!) times for guaranteed producer regime.  Yes, MN3207 is operating at a frequency of up to 2-2, 5 MHz, but how? ... I think is bad …

That is why device at MN3x07 never will work the same way as device at SAD1024.

Thomas, I just said! 

Igor

[Thomeeque]

But to get the same delay will increase MN3207/3007 Fclock in 25/50 (!) times for guaranteed producer regime.

 I believe it's half (12.5/25)

Yes, MN3207 is operating at a frequency of up to 2-2, 5 MHz, but how? ... I think is bad …
 That is why device at MN3x07 never will work the same way as device at SAD1024.

 Yes, it probably will not, but it still might be interesting..

 E.g. at 1.4MHz it works quite well and it's 7-times (14-times in case of MN3007 and I believe in A/DA with 3007 retrofit it's used at similar frequencies) over the limit stated in datasheet, so..

Thomas, I just said!  

 And I just responded

 Btw. MIC4424 looks like very interesting chip, unfortunately sourcing it looks problematic (none of shops around me sells it, which is something I use as a "criterion" for choosing reasonably obtainable parts)

 T.

[Thomeeque]

But if the output MN3102 to fix an additional buffer (4049) as in the diagram by Thomas from the first message, everything is great!

 So, I wonder how this Wave Forming block inside MN3102 looks like, maybe it's something relatively simple and we could (maybe at least partially) implement it externally and put between 4013 and buffer (without need to adopt whole clock for MN3102)..

EDIT: I'll ask in separate thread (Wave Forming block inside MN3101/2)..

 T.