Author Topic: Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep  (Read 10265 times)

savethewhales

Re: Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep
« Reply #80 on: September 29, 2020, 08:04:45 AM »
First just wanted to say sorry for taking so long, a job appeared and it took me off here for some time.
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If you set the pot to half-way there is Rpot/2 from the wiper to one end and Rpot/2 from the wiper to the other end.  Thevenin equivalent resistance is those two in parallel so Rpot /4.

Ok!

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Yes it does add the DC from the trimpot with the LFO.

This is important. I've been searching more and more and by looking about the astable multivibrator circuit, I understand that to get a triangular output, with the circuit of the P90, I HAVE to have some kind of feedback to the input DC, because the triangular wave output will "trigger" the state change of the multivibrator, am I correct?

Now smth I'm thinkin now, is if I use a integrator following the astable multivibrator circuit, in this case an op-amp integrator, I could be able to get a triangular wave without messing with the input DC, does this make any sense?

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The MXR circuit is already doing that.    If you want to see how the circuit performs run you spice simulation with the at 9V and at 7V and look at what happens to the LFO.   In this case you might want to reduce the voltage of the zener when at 7V because in reality the zener voltage will drop.

I just did the sim, and it gives me a lower voltage span on the LFO... Really it does make sense, as it's changing also the current that goes to the timing cap.. right?

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The other thing you can do is compare two designs.  You set-up the two circuit to be equivalent at 9V then you change the supply to 7V and look at how the gate voltage is changes.  One will change less than the other.

Wait, I didn't get this, what two designs?

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Unfortunately coming up with a better design is a whole project in itself.     There's many ways to do it.   A very simple way to make the circuit tougher against supply variation is simple to regulate the power supply!   Ideally you would want to regulate the supply without lowering the headroom of the audio circuits.

Of course, it makes sense. I brought up an idea above, that I think would work.. I'm going to simulate it as soon as I can.
Btw, I'm going to use a 9V power supply (the one that connects to the wall hahah) so I think it would be "regulated", and when you talk about the headroom I can only think about the usual 100mV peak headroom of the jFET's... It would block any attempt of mine to get more headroom, I'm guessing.

savethewhales

Re: Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep
« Reply #81 on: September 29, 2020, 06:45:56 PM »
Hey guys,

So, I'm trying to experiment with this LFO circuit, that in theory can give me a triangular LFO without all that DC bias stuff:

However, when I simulate it on LTSpice, with the circuit below:

I get no square nor triangular wave on the output, just like I will show:

This is happening no matter what initial condition I put/don't put.. Also I've changed the Vcc values, changed the reference to a bigger voltage and nothing.. Could I be doing something wrong or is it not supposed to work?

Later I've tried to sim another triangular LFO circuit, as following:

And yet again I can't seem to get a good transient response.. even with the initial times on.. wth! Can somebody help please?
Smth is going on and I don't know what.
« Last Edit: September 29, 2020, 07:18:27 PM by savethewhales »

Rob Strand

Re: Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep
« Reply #82 on: September 29, 2020, 08:39:09 PM »
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And yet again I can't seem to get a good transient response.. even with the initial times on.. wth! Can somebody help please?
Smth is going on and I don't know what.
Have a look at the schematics for the Boss CE-2 Chorus or the Boss BF-2 Flanger and see if you can find your mistake.
The internet:  answers without the need for understanding.

savethewhales

Re: Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep
« Reply #83 on: September 30, 2020, 05:25:49 AM »
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Have a look at the schematics for the Boss CE-2 Chorus or the Boss BF-2 Flanger and see if you can find your mistake.

Looking at the circuits, I'm afraid I couldn't find the mistakes I've done... Actually, I've taken the circuits I simulated from sites which explain them, the sites are:

https://kassu2000.blogspot.com/2015/10/variable-waveshape-lfo.html?m=1

And

Now this last one even has a online simulation, where I could change the values of resistors and see what happens to the circuit. I basically did it just like it is on the website, and nothing.. I can seem to understand what goes on, so as I'm going to use an oscilloscope today, maybe I will see if I can make the circuit oscillate..

It's just I wanted to make an oscillator without the Vbias mambo jambo, or in other words, something fixed, derived from an astable multivibrator (as this last one is) as far as I'm concerned

Rob Strand

Re: Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep
« Reply #84 on: September 30, 2020, 05:54:34 AM »
Compare your circuit to this, and see if you can see the problem,

https://www.hobby-hour.com/electronics/s/schematics/boss-bf2-flanger-schematic.gif

The internet:  answers without the need for understanding.

savethewhales

Re: Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep
« Reply #85 on: September 30, 2020, 06:25:22 AM »
Compare your circuit to this, and see if you can see the problem,

https://www.hobby-hour.com/electronics/s/schematics/boss-bf2-flanger-schematic.gif

Sooo.. Virtual ground? If so, I already tried to do with and without, and nothing...

Rob Strand

Re: Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep
« Reply #86 on: September 30, 2020, 06:43:02 AM »
Yes, virtual ground, because it is a single supply.  Another thing is I think you entered 220K into the part designator field (ie. R1, R2, etc) instead of the value field.  Which is currently 1K not 220K.
« Last Edit: September 30, 2020, 07:47:14 PM by Rob Strand »
The internet:  answers without the need for understanding.

savethewhales

Re: Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep
« Reply #87 on: September 30, 2020, 08:57:43 AM »
Yes, virtual ground, because it is a single supple.  Another thing is I think you entered 220K into the part designator field (ie. R1, R2, etc) instead of the value field.  Which is current 1K not 220K.

Yes and yes. I was dumb.
Was putting 15v and 0V for supplies, while not using virtual ground on the inverting/non-inverting...

savethewhales

Re: Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep
« Reply #88 on: September 30, 2020, 11:08:30 AM »
I am now beside a oscilloscope and I'm able to tell what's the differences bewteen the circuits that we were just talking (with and without virtualground/with and without dual supply, etc. ).

Here it is the circuit with +-15 Volt and ground on the non inverting:

And here it is the circuit with the battery and the Vreference of around 4.8 Volt (I moved it down to be centralized, but the values can be seen down low (minimo=minimum, and maximo=maximum).

As I can see, I can use a voltage reference to make a DC offset, and I can make the span lower or higher for my taste, however I can't seem to find a solution to put this thing going between 3.5 and 4.6 Volt... With a Zener I feel like I would be badly served because mine is 5.1 Volt.. Is there any way I can get around that? Maybe doing a voltage divider from the Zener just like the P90, but without the whole DC bias stuff?

Rob Strand

Re: Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep
« Reply #89 on: September 30, 2020, 08:28:35 PM »
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As I can see, I can use a voltage reference to make a DC offset, and I can make the span lower or higher for my taste, however I can't seem to find a solution to put this thing going between 3.5 and 4.6 Volt... With a Zener I feel like I would be badly served because mine is 5.1 Volt.. Is there any way I can get around that? Maybe doing a voltage divider from the Zener just like the P90, but without the whole DC bias stuff?

The 100k and 56k set the Schmitt trigger thresholds.

For you +/-15V case in the link:
- Supply +/- 15V
- Opamp output swing about 1V less than power rails, so +/-14V
- Schmitt trigger voltages are the voltages at the out of the 56k + 100k divider
Vt = +/-  14 * 56k / (100k + 56k) = +/-5.02V   ;  that agrees with you simulation.

A slightly different way to look at it is to separate the DC level and the *change* in the output level.
The input to the divider swings -14V to 14V, a total change of 28V.
The change in voltage at the output of the divider is 28V * 56k / (100k + 56k)  = 10.05V ; which agrees with 2x5.02V

The change in the Schmitt trigger sets the change in threshold and also sets the change in the peak to peak output of the triangle wave.

For your 9V case with DC offset,
You currently have 3.68V to 6.16V  which is a change of 2.48V
But you want  3.5V to 4.6V, which is a change of 2.1V

You want to reduce the change by a factor of 2.1/2.48  = 0.847.

The way to reduce the swing at the output is the modify the Schmitt trigger levels.   You want to reduce them

If we go back to your +/- 15V simulation.
The 100k + 56k divider sets the Schmitt trigger levels.   To reduce Schmit trigger them we could for example decrease the 56k.
If you set the 56k to 43.7k the voltage change at the output of the divider is,
28V * 43.7k / (43.7k + 100k) = 8.51V

This reduces the swing by a factor of 8.51/10.05 = 0.85.

If you modity the value in you falstad similation you will see it works.

If you use these new values on you 9V circuit you will find the change in the output is close to what you want.  It will be a bit low because the opamp doesn't swing to the full supply and this affects a 9V circuit more than a +/-15V circuit.   So you may need in increase the value from 43.7k.

Once you get the change in the output correct you can use the DC offset to shift it so the actual voltages are where you want them.

The way I've describe it above is to take something that is nearly correct and tweak it.   You can actually calculate the required divider ratio and the 43.7k resistor from maths without ever build a trial circuit.   Look up how to calculate Schmitt trigger levels.  I think I already explained this.

I mentioned this before, when you use the DC offset you will find the output duty cycle changes.   The time to rise-up is no longer the same as the time to fall-down.    That's another reason why the MXR pedal separates the DC bias and the LFO.

The internet:  answers without the need for understanding.

savethewhales

Re: Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep
« Reply #90 on: September 30, 2020, 08:50:47 PM »
As soon as I can I will answer this accordingly, but for now I just wanted to say I managed to get the 3.5-4.6, volt span, by having 18k to ground and 100k making a divider with it (which gives me 1.1 volt span), and then I used 4.8 V from the zener (5.1 V zener with a 3.3k resistor) and then at the end of the LFO I used an op amp to buffer plus a resistance dividing at the end with 56k to ground and 10k.

Anyway, I'm getting the results good but the response of the triangle gets a flatter edge sometimes and I don't know if it is wiring problems or what.. When I can I 'll show you.

savethewhales

Re: Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep
« Reply #91 on: October 01, 2020, 06:56:32 AM »
So,

For this exact circuit (except for the zener that is different):

I get this transient sim (clean as F):

Now, these are the results I'm getting out of the testing on oscilloscope, and I'm kinda worried not knowing what to do or what causes this (notice that I already checked every single point and changed wires everysinglewhere, but none changed) -

Output:

Output of the capacitor C2:

non inverting input of the first op-amp:

Output of the op-amp (could be better):

Evidently The square output on the non inverting is not reeeally a square wave, but I don't think that is supposed to be causing the output """triangle""" that I'm having.. Can somebody help me please?

Thanks.

savethewhales

Re: Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep
« Reply #92 on: October 01, 2020, 07:19:34 AM »

The 100k and 56k set the Schmitt trigger thresholds...

...For your 9V case with DC offset,
You currently have 3.68V to 6.16V  which is a change of 2.48V

True! I actually was doing that yesterday and I found ot that with the 9V single supply with a voltage reference on the virtual ground, I was needing a 18k resistor  (the closest to real values) to get my LFO as I wanted.

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But you want  3.5V to 4.6V, which is a change of 2.1V...

...If you modity the value in you falstad similation you will see it works.

Just one thing, the change I want is 1.1 V not 2.1 (3.5 to 4.6).

However, yeah, of course, I did exactly what you're sayng, changed values on the virtual simulation of the site and saw how they went and then did math to find the exact values.

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If you use these new values on you 9V circuit...
...That's another reason why the MXR pedal separates the DC bias and the LFO.

Exactly! You already explained the schmitt trigger levels (and I learned how to do it on the internet at the same time). Any way it does make sense that it affects most the 9V single supply.
My duty cycle as I put on the post above, is really messed up.. Don't really know what to do now..
When you say separating the DC bias and the LFO you mean those big 3m9 and 1m resistors?

Rob Strand

Re: Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep
« Reply #93 on: October 01, 2020, 07:21:42 PM »
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Evidently The square output on the non inverting is not reeeally a square wave, but I don't think that is supposed to be causing the output """triangle""" that I'm having.. Can somebody help me please?
The 'tilt' on the square-wave is due to the AC coupling on the oscilloscope, not the circuit.

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Just one thing, the change I want is 1.1 V not 2.1 (3.5 to 4.6).

There is a problem with trying to get down to 1V directly from the opamp.      Some opamps don't work when the inputs are too close to the either the positive or negative supply rail (or both).   It's called the common-mode range in the opamp datasheet.   For the Schmitt trigger to work  the opamps have to operate with their common mode -range.   For many opamps the lower limit is 2V from the negative rail so that means trying to get a 1.1V threshold won't work.    One option is to use a different opamp, one that has a common-mode range that is closer to the negative rail.   The other way is to use a circuit similar to the 1M + 3.9M used on the MXR phase.  In this case the 1M side can be tied to a low voltage to lower and shift the DC point down at the output.  The LFO is then designed with higher voltage levels, which are within the opamp's common mode-range.

The take home message is when you change circuits you need to be aware of all the hidden factors.   The original circuit might work but a modified circuit might not because you haven't considered all the factors affecting the performance.    In this case it's the common mode range.    That doesn't always mean it can't be done.  You can change the opamp to a different type, one that has a common-voltage closer to zero.

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When you say separating the DC bias and the LFO you mean those big 3m9 and 1m resistors?
Yes.

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My duty cycle as I put on the post above, is really messed up.. Don't really know what to do now..
It's not straight forward to fix, especially when the LFO frequency needs to vary  with a pot.

The problem is this:
When you lower the Scmitt-trigger levels  the timing cap voltage is much lower (say 3V).    When the cap is discharging, it discharges towards 0V from 3V..   However the cap charges, it charges towards about 9V, that means there is (9V-3V) = 6V across the timing resistor.   The capacitor will charge-up quicker than it can discharge.  So by nature the rising part will be shortened.

The root of the problem is the opamp output is swinging to approx 9V.   If you wanter to solve this problem you would need to limit the output swing of the opamp.   So tat can be done by reducing the supply voltage.   Or you can feed the output to a zener diode with a series resistor to clamp the output voltage.   There's many ways to do it.

I believe  original idea was to make the simplify the circuit by trying to get the DC bias directly off the LFO, so you could remove the bias pot (and 1M resistor).    However that's caused a whole lot of new problems and to fix it you have to add more part's than you saved.     That's why people end-up using the MXR type circuit!
« Last Edit: October 02, 2020, 12:17:40 AM by Rob Strand »
The internet:  answers without the need for understanding.

savethewhales

Re: Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep
« Reply #94 on: October 02, 2020, 07:24:09 PM »
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The 'tilt' on the square-wave is due to the AC coupling on the oscilloscope, not the circuit....

...There is a problem with trying to get down to 1V directly from the opamp.

...It's not straight forward to fix, especially when the LFO frequency needs to vary  with a pot.

...That's why people end-up using the MXR type circuit!

First sorry being late, I have been crazy working on the physical tests of the circuit, which are only possible when I go to my college, which is far from home, you get the scene.. Anyway I have good news.

I have an idea of having messed with the ground after that and being able to keep the output triangle without the tilt..
Either way I wasn't satisfied and went to do another circuit, based on the first on I put here.

With this one, I was able to get the voltage range that I wanted, as well as having a nice triangle on the output without failing on rise/fall etc.

I'm not yet sure if it really was cables problems/ground problems/smth else. All I know is it worked and I even put a potentiometer of 470k to determine the ranges. The maximum value gives me less range and the minimum value is the opposite.

Here's the circuit:

I got the output out of a voltage divider to pull down the DC offset.

Here are the image taken from the oscilloscope at maximum and minimum range, respectively:

I still haven't decided what frequency range I will want on the LFO, but I believe between 0.3 and 8 Hz will be good and "do-able" with this circuit (500k pot on the place of R4).

I read everything that you said Rob, for what you said I thank you a lot.
If problems happen with my LFO I'll be sure to start thnking and simulating what you told me. There's some reason why they do it like MXR.. I had to go this far to understand it, but if had not come here, I would still not be understanding a single thing of the P90 LFO.
...
As for the main circuit (from the input to the summing of the wet+dry signals), I unfortunately am having headaches because it just won't work no matter what I do. I imagine it has to do with cables or smth. I spent the whole day trying to understand the why's, without having any answer...

Before what's down here, Wanted to be clear that the simulations are all ocurring accordingly, and nice (even if I take off some elements which I will mention below).

The circuit is down here:

However I haven't build the whole circuit on bread, I left out two stages of phase shifting (just to see what one would give me) and I left out the output op amp (because I didn't really want gain).

Is there any way that I can make the circuit work by testing different parts of each time? And what parts? Because like if I leave only one all pass filter, I have no change on the output, and I wouldn't know if it's doing correctly..

I'm just really lost and already thinking on the possibility of having to buy the pcb without really knowing that the circuits works.

Regards, Fred

Rob Strand

Re: Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep
« Reply #95 on: October 03, 2020, 07:33:51 PM »
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Anyway I have good news.

With this one, I was able to get the voltage range that I wanted, as well as having a nice triangle on the output without failing on rise/fall etc.

I'm not yet sure if it really was cables problems/ground problems/smth else. All I know is it worked and I even put a potentiometer of 470k to determine the ranges. The maximum value gives me less range and the minimum value is the opposite.

Here's the circuit:

I got the output out of a voltage divider to pull down the DC offset.
You did well.    That way should work.

If you put in JFETs with larger VP and adjust the divider to set the bias the LFO output at the divider will get smaller.  The larger VP JFETs actually need bigger LFO swing to get the same resistance range..    The MXR keeps the LFO output constant, which still isn't correct.

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As for the main circuit (from the input to the summing of the wet+dry signals), I unfortunately am having headaches because it just won't work no matter what I do. I imagine it has to do with cables or smth. I spent the whole day trying to understand the why's, without having any answer...

Before what's down here, Wanted to be clear that the simulations are all ocurring accordingly, and nice (even if I take off some elements which I will mention below).

However I haven't build the whole circuit on bread, I left out two stages of phase shifting (just to see what one would give me) and I left out the output op amp (because I didn't really want gain).

OK let me get this straight.  The sims look OK but the actual breadboard isn't working

Measuring the DC voltages at the output of all the opamps is a good start to identifying problems.   The DC voltage should be Vref.

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Is there any way that I can make the circuit work by testing different parts of each time? And what parts? Because like if I leave only one all pass filter, I have no change on the output, and I wouldn't know if it's doing correctly..

Yes, the only thing you have to be careful about is when you separate part of the circuit it might not work because it needed the DC voltage of the previous stage to bias the opamps correctly.  Also if you connect a signal generator without *adding* a coupling cap  to the input it will connect that input to 0V in a DC-sense and complete stuff-up the biasing.    If you are careful about those aspects you can easily separate the parts.   If you don't do it right you will have more headaches than you already have.

Another approach would be to replace the JFETs withs with fixed resistors, say 3k3 to 4k7.   For two stages that will put the notch at 1kHz.   Put a 3kHz signal on the input.  One important thing is you might need to keep the signal level to about 100mVpk otherwise the JFETs could distort the signal.  Connect channel 1 of the oscilloscope to the input signal.  Then use channel 2 to look at the outputs of the opamps from left to right on the schematic.  Compare the level and phase of the signal.

If you want to see what you expect you can actually set-up the same circuit in LTspice.

To check the mixer you try lifting disconnect the 150k to the last all-pass filter and see the output of the mixer is just the inverse of the input signal..  Then replace the 150k and  disconnect the 150k to the input buffer and you should see the output of the mixer is the inverse of the signal at the last all-pass filter.

Connect both 150ks and sweep the signal generator frequency and see if you can find the notch at 1kHz.

If you get that far you know the signal is passing through all the stages correctly.

Put the JFETs back in.   Connect the gate to a trimpot so you can adjust the bias to get the notch at 1kHz.   Measure the Vgs voltage to make sure it corresponds to about rdson =  3.3k ohm.   Check against the LT spice sim.

Finally put back you LFO.   If you have trouble now you know it's not the opamps or the JFETs.  It probably something to do with the DC level from the LFO.
The internet:  answers without the need for understanding.

savethewhales

Re: Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep
« Reply #96 on: October 04, 2020, 06:00:27 AM »
You did well.    That way should work...
... The MXR keeps the LFO output constant, which still isn't correct.

Quote
OK let me get this straight.  The sims look OK but the actual breadboard isn't working...
... It probably something to do with the DC level from the LFO.

Wow I don't even know how to thank you. For now, THANK YOU!

About the last sentence, I didn't connect the LFO to the main circuit (because the analyser can't do a frequency response with the LFO varying), so I put a fixed voltage coming from the zener divider going to the gates.

Another thing is, what is that of the capacitors on the input? I should connect them right after the input signal, and then in series with the main circuit?

I'm going to college right now to use and test the circuit, so I'll be putting updates here regarding this.
Later

savethewhales

Re: Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep
« Reply #97 on: October 04, 2020, 08:43:21 AM »
Right off the bat, I was getting a distorted sinusoid on the input, not even the output..
Actually the output "seemed" better because the scale was bigger.

the circuit I started testing is this:

And the input wave is shown as follows:

Could it be that it's because I didn't put a capacitor on the input?

*EDIT*: Managed to get nice and clean waves. The problem was the amplitude of minus than 100mVp, it gave me too much noise.. (the following has 1V peak on input):

« Last Edit: October 04, 2020, 09:58:35 AM by savethewhales »

savethewhales

Re: Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep
« Reply #98 on: October 04, 2020, 07:32:01 PM »
Good news here,

I was able to build the circuit on bread and see it work (with resistors on place of the FET's and with the FET's). First I build with one fiter only to measure the DC voltages. As I saw 4.8V on the op-amp outputs, I went to build one more filter to be able to make the notch. When I saw 4.8 Volts on outputs of this new op amp after building (after this circuit:)

, I decided to go and see it on the oscilloscope:

With resistors (both 47k):

I had a cut frequency of 213 Hz, just like I calculated (with the equation "fnotch=(tan(90/2))/(2.pi.c.rparallel)", just like the one that is shown on electrosmash explanation. Actually it's important to say that the 90º is in each filter, which leads to 90+90=180 (as I build it with only 2 all pass filters, aka 1 stage).

After seeing it had worked with resistors , went on and put the jFET's, but alternatively to putting pot's, I simply made a divider to have -1.3 Vpinch off (which is what I had measured).

Here are some screenshots of the sims on the osciloscope:

What I wanted now was to use a pair of FET's (reportedly -1.3 Vpinch off) with Vgs on pinch and on 0V and see on Audio precision what the frequency response was.

-1.3 vgs
notch around 173 hertz
Which is equal to rds=aproximattely 100kohm

0 vgs:
notch around 22khz
Which is equal to rds=150 ohm

Now the same process substituing for other 2 FET's with measured vgs of -1.3

-1.3 vgs
notch around 170 hertz
Which is equal to rds=aproximattely 100kohm

0 vgs:
notch around 23.5khz
Which is equal to rds=150 ohm

All of this was very important for me to do because I could see that the results of rds were not even close to what I measured (after all the methods used I got around 320 ohms), what means that only by doing this type of test was I able to see how my recent bought FET's responded.

I didn't even had much time from the moment I made the circuit work, so I couldn't test exactly if the vpinch-off of those FET's was really -1.3V, or if it was different too (but making the calculations it seemed correct).

Now besides all of that, and after seeing the images, I wanted to know what is that attentuation that I have on the low frequencies (-6dB on the 20Hz)? I made calculations to not lose audio frequencies, and that counts to the input DC filter (with the capacitor). Did I calculated wrong? The resistor R3 doesn't enter on the equaton right? Or am I missing something?

Oh and btw, the 6dB gain overall is desired (summing amplifier with 150k on the negative feedback).

PRR

Re: Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep
« Reply #99 on: October 04, 2020, 08:33:09 PM »
> what is that attentuation that I have on the low frequencies (-6dB on the 20Hz)?

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