Afraid I have nothing positive to add, but am starting to get a theory of it...
2 things:
I think modulating pin 2 could be causing "crowbar" latch up of the chip. Theory is, internally, the circuits have some capacitance. Normally the reference voltage on pin2 is half supply, so about 2.5v. When the LFO raises the voltage, anything internally with 2.5v charge gets lifted with it, potentially exceeding the power supply (2.5v+LFO increase). The same thing again to the neg supply when the LFO pulls pin 2 down. This can usually cause latch up with most MOS chips. Together with that, there could be a charge pump action going on via stray or designed PN junctions in the chip, generating excessive voltage versus supply. Since it's happening internally, you probably can't do anything about it, such as adding 2 reverse clamping diodes between pin2 and +5 and Gnd-
but it could be worth a try?
The second worry, is that we don't know how much current pin6 can really, safely, sink. Recommended minimum 1k delay resistor is 2.5mA - that's about the limit for most MOS devices (such as standard gates) that aren't designed specially for higher current sinking.
Well, maybe a 3rd point, you could be too close to solar flares or the microwave...
http://en.wikipedia.org/wiki/Latchup