What's the real story on SOURCE v/s DRAIN trimmers in JFET circuits?

[Eb7+9]

I want to express an idea to see if it rings a bell:  the two *main* JFET parameters that define the response of a particular JFET are the
Further investigation show that for JFETs with the same part number, there is a definite and fixed relation between IDSS and VP.  This can be seen in graphic form in J201 and 2N5457 datasheets (Fairchild manufacturer, 3rd page).  In other words, when a datasheet indicates VP from 0.3 to 1.5, and IDSS from 0.2mA to 1mA, it doesn't mean you can have a JFET with any pair of VP and IDSS values withing those ranges.  These parameters are in fact "tied" by a definite relation, which is approximately IDSS=a*(VP^b), where 'a' and 'b' are constants that correspond to that particular device family.

number one assumption made going over jFET device data - where the datasheet shows the "typical" Idss-Vgs(off) curve ... this is a middle-of-the-road curve, if the data was properly shown as a Gaussian cloud around that curve it would dissuade people from working with these devices and thus buying them ... a device "lot" is said to be tight when all devices can be assumed to lie very closely together to such a curve ... the assumption that one's lot is tight is what usually leads to serious questioning afterwards in practice ... it would be nice if Vgs(off) and Idss did track but they don't always in general - at least systematically - hence the reason why people test for both parameters ... things possibly can get even worse when devices are not from the same lot, but still within a lot considerable variations exist otherwise ... again, this has a marked impact on VCR applications - a 15%~20% variation in Vgs(off) leads to around x100 variation in max resistance in a swept voltage application (ie., phasors) ...

[wampcat1]

I think this thread has made me realize who I do and do not want to party with.

[John Lyons]

 



Touche Brian!



john

[aron]

OK guys, lets try and keep this one on topic since there are some really good technical examples in here.

[stm]

Well, if that's correct, you have just reduced two handles down to one handle.

Now we just have to figure out how to grab hold of it.

Exactly!

[stm]

I want to express an idea to see if it rings a bell:  the two *main* JFET parameters that define the response of a particular JFET are the
Further investigation show that for JFETs with the same part number, there is a definite and fixed relation between IDSS and VP.  This can be seen in graphic form in J201 and 2N5457 datasheets (Fairchild manufacturer, 3rd page).  In other words, when a datasheet indicates VP from 0.3 to 1.5, and IDSS from 0.2mA to 1mA, it doesn't mean you can have a JFET with any pair of VP and IDSS values withing those ranges.  These parameters are in fact "tied" by a definite relation, which is approximately IDSS=a*(VP^b), where 'a' and 'b' are constants that correspond to that particular device family.

number one assumption made going over jFET device data - where the datasheet shows the "typical" Idss-Vgs(off) curve ... this is a middle-of-the-road curve, if the data was properly shown as a Gaussian cloud around that curve it would dissuade people from working with these devices and thus buying them ... a device "lot" is said to be tight when all devices can be assumed to lie very closely together to such a curve ... the assumption that one's lot is tight is what usually leads to serious questioning afterwards in practice ... it would be nice if Vgs(off) and Idss did track but they don't always in general - at least systematically - hence the reason why people test for both parameters ... things possibly can get even worse when devices are not from the same lot, but still within a lot considerable variations exist otherwise ... again, this has a marked impact on VCR applications - a 15%~20% variation in Vgs(off) leads to around x100 variation in max resistance in a swept voltage application (ie., phasors) ...

I agree that "typical" curves can be "pretty" versions of reality.  Nevertheless in my experience from the many different JFETs I have measured (J201, PN4392, J111, MPF102, 2N5457, 2N5458) I can confidently say there is a strong correlation between VP and IDSS, in other words, increasing VP means increasing IDSS values.  In fact, this relation appears pretty straight when the IDSS v/s VP graph is log-log, suggesting a power-like relationship.

Even though IDSS values do not fit perfectly to the ideal curve, this dispersion is bounded so it still allows for some useful results.  IME we are talking about +/- 10% variation from the theoretical value.  If we disregard curves entirely, then the hybrid biasing proposed in Siliconix AN-102 should be disregarded as well, as it relies on using typical curves and expected minimum/maximum parameters.

Regarding the use of JFETs as voltage controlled resistors, I agree that VP is the most important parameter to consider for this particular application.  When you match JFETs for VP, then resistance variations due to variations in Rds(on) or VP/IDSS are surprisingly small.

[Eb7+9]

yes, life's one great jFET device theory party ...

if you compare Idss-Vgs(off) data curves for different device types, ie. between manufacturers, you'll find they don't have the same profile or even concavity ... the random variations overall is shown to be process dependent and not wholy systemic on physical principles - this makes sense to me ... log-log domain or not the profile is not linear and therefore the relation is not systemically proportional - otherwise that would be stressed in textbooks ... IME Idss and Vp can vary by factors of several 100% - if you use a match-test method that has NFB in the source circuit then the "test voltage" values you get of course can easily be of the order of 10% provided there's enough NFB ... that's why such test methods are considered bogus and never mentioned in manufacturers app notes - otherwise they'd be ...

Regarding the use of JFETs as voltage controlled resistors, I agree that VP is the most important parameter to consider for this particular application.  When you match JFETs for VP, then resistance variations due to variations in Rds(on) or VP/IDSS are surprisingly small.

just to be clear minimum Rd is a function of both Idss and Vp - again, IME I've found Rd min variations to exceed factors of 3 or 4 ... it all depends on the devices you have to play with - one might be lucky and be dealing with a tight set but you only really know until you write down your number pairs ... Vp is not most important as far as the benchmark "min" value goes, both variables have near equal weight in that equation ... I'm referring to how the range of controllability is affected by variations in Vp ... this is why phasors only typically traverse through one decade of resistance change and are not typically used for large-valued resistance ranges (this is one area where opto-couplers blow jFETs away) ... and the reason why we see low valued (~20k) shunt resistors across VCR jFETs in phasors ...

when you use a Drain load trimmer to set the bias voltage in the Drain circuit you are not affecting bias current nearly as much as you would if you were trimming the Source resistance ... also, I don't see why output impedance is a big concern in jFET circuits since we're typically looking at a largish resistance level in the successive stage - unless drive impedance plays an important role in the driving the Gate diode when turning it on to produce clipping effects but then again bias trimming in the Drain circuit never involves driving down the load resistor that much across the linear bias range ... in my jFET overdrivers (Meteor and modded versions) I haven't seen any instance of distortion or tone quality change by varying the loads ... I really think that tube-amp-schematic simulations are not biasing jFETs for optimum noise - and I think it has to do with this propensity to bias in the Drain circuits and neglect the potential for achieving similar gain ratings but at lower bias current settings ... again, the app notes make clear that jFETs are known for yielding higher voltage gains at lower bias levels ... the obvious question then is why insist on biasing at higher currents, only to lose some available gain and yield more noise ?

[R.G.]

I hate to mention it, but there's an existence theorem in play here.

There have been some decades of Really Smart Guys trying to make JFETs tractable. Guys who live and breath semiconductor physics in the office next to the guys who've designed analog for their entire professional lives, and many such pairs, with big money and professional prestige to be had. If there was a simple underlying principle to get JFETs to behave, it is likely that it would have been found. That doesn't mean it does not exist - but the odds make winning a trifecta seem like a sure thing.

No matter how many (or how wet) pipe dreams you have about designing a priori Fet-for-tube replacements for Fender vibratos and other esoterica, the variations of JFETs from the factory will almost always make you use trimmers, use selective components, or JFET selection.

JFETs vary. Expect it. Roll with it or design around it.

[earthtonesaudio]

I know everyone's been talking about the class-A common source configuration, but there are other ways of making gain from JFETs...

What about common gate?  If you use it as a current follower you can get voltage gain which is independent of device characteristics.  Then you just slap some source followers on the input and output, which gives you current gain while simultaneously providing good input/output impedances.  If you're willing to add the complexity of two more transistors, you can get power gain without phase inversion which is tolerant of device variations.

I have this on the breadboard right now, and it's proving to be surprisingly easy to tweak, even without coupling capacitors.  Right now it's two MOSFETs followed by one JFET, but I'm working on all-JFET and BJT/Darlington versions next. 

I don't know if anyone would be interested in exploring this more, but if so I can start another thread with some pretty pictures and stuff.

[aron]

Alex,

Sounds good to me.

[alanlan]

I'd be interested to know also, but my first doubt (without any justification really) is that it won't solve the fundamental problem of reliable, reproducible biasing but I'm saying this in the hope that you'll show me the light!

[alanlan]

Feel free to start another thread but something else just occurred to me (you've really got the juices flowing on this one):

If you look at a common gate amplifier, the signal is applied to the source and requires a fairly low impedance driver.  OK, fair enough, and the signal on the source modulates vgs  to vary id which can then develop a voltage across a load RL or be fed into a current to voltage convertor etc.

But isn't a common source with Rs very similar i.e. we use the high impedance gate input for our signal which the source then follows (but not with quite unity gain) so there is a vgs signal which modulates id and, well, you know the rest.

So does the common gate really achieve anything useful?

[R.G.]

There is no difference to the biasing arrangements whether you use common source, common gate, or common drain. They can all (potentially at least) be done with exactly the same resistance arrangements, only the caps rearranged for input, output, and 'commoning'.

[Eb7+9]

So does the common gate really achieve anything useful?

common gate, common base, common grid ... are all current followers : low Z-in, high Z-out ... current gain near or equal to unity ... if you look at them from a voltage point of view they won't seem useful ...

[Ben N]

low Z-in, high Z-out ... current gain near or equal to unity ...

Did you mean voltage gain?

[R.G.]

common gate, common base, common grid ... are all current followers : low Z-in, high Z-out ... current gain near or equal to unity ... if you look at them from a voltage point of view they won't seem useful ...

The primary use for common gate/base/grid is for power gain at RF with high isolation between input and output. With the control element grounded, there is a much smaller feedback capacitance.

Voltage gain may be large, as may power gain, because of the difference in impedances. It takes quite a small voltage to make a given current flow in the low impedance seen at a BJT emitter-to-base. But that same current happens at what could be very high voltage on the collector.For instance, if you have an NPN set up with base grounded, emitter pulled down by just enough to turn the transistor on, and you then force a 10ma change into the emitter, it may only change the emitter voltage a fraction of a volt. But the collector can be supplied by a couple of hundred volts, and that same current change appears at the collector and across any collector load. So the voltage gain may be large.

The only issues with common-control-element circuits is that the input side is quite difficult to drive in the normal voltage-centric sense because it is quite low impedance.

The next biggest uses of common base/gate/grid is for level shifting and cascoding. You tie the control element to a fixed voltage, then use changes on the emitter/source/cathode to make same-current but much different voltage loads. In cascodes this happens, but the control element can be grounded for AC purposes and fixed for DC purposes. Music Man amps used a 30V JFET as an input amplifier, and cascoded its drain with a tube to keep damaging voltages off the drain of the JFET. The tube took the voltage stress and reflected the signal current to the much higher B+ for the tube.

[alanlan]

So does the common gate really achieve anything useful?

common gate, common base, common grid ... are all current followers : low Z-in, high Z-out ... current gain near or equal to unity ... if you look at them from a voltage point of view they won't seem useful ...

Yes, I know that but it has been suggested that the common gate is the answer to all our biasing problems, which is what this thread is about.  I'm interested to know how it answers our collective "problem".

[earthtonesaudio]

I don't mean to make common gate as a panacea for JFET biasing problems, mainly because the amplifier you end up with is quite different from the common source amplifier, and nowhere near a 'class A triode' type of amplifier.   Plus, the prototype on my breadboard right now works, but it doesn't sound good (yet).

That being said, there are a couple ways to bias a common gate amplifier.  You can bias it like a voltage amplifier or as a current follower.  The difference being (as far as I can tell in my reading so far) the size of the source resistor and hence the input impedance.  As Rsource becomes smaller, the circuit acts less like a voltage amplifier and more like a current follower, or something like that... but the real point to making Rsource smaller is that it removes the device coefficients from the gain equation.  Then the voltage gain becomes Rdrain/Rsource (I think I'm remembering that right... I'll have to go back to Wikipedia... )

Yes, the obvious problem is the impedance matching.  If only there was a simple buffer circuit which has high Z in and low Z out... Oh yeah, the source follower does that!  You need one at the input so you can plug in a guitar, and one at the output so you can drive whatever might come later in the signal chain. 

The price you pay for splitting the voltage and current gain into different devices brings the tally up to 3 transistors, and if you're clever about biasing you might not need coupling caps between them.  The Rsource for the common gate and the first source follower can be the same resistor, and if you hook up the second source follower like a SRPP output stage, then its source resistor can pull double duty as Rdrain for the common gate stage, and Rsource for the output source follower.  If you make it variable it's a gain control.

New thread with pictures coming up soon, I promise.

[R.G.]

So does the common gate really achieve anything useful?

common gate, common base, common grid ... are all current followers : low Z-in, high Z-out ... current gain near or equal to unity ... if you look at them from a voltage point of view they won't seem useful ...

Yes, I know that but it has been suggested that the common gate is the answer to all our biasing problems, which is what this thread is about.  I'm interested to know how it answers our collective "problem".

You're right, alan. The use of common source/drain/gate has almost nothing to do with biasing predictability. It is possible to take the exact same circuit of resistors and JFET, and get all three types of circuit by merely rearranging where the signal comes in and goes out, and which terminal is "grounded" by a cap to ground.

There is nothing inherent in "common-gate-ness" that solves bias issues of itself.

[Ben N]

**WARNING: LITERARY ALLUSION**

It is possible to take the exact same circuit of resistors and JFET, and get all three types of circuit by merely rearranging where the signal comes in and goes out, and which terminal is "grounded" by a cap to ground.

Kinda like the Soldier in White?  (Catch-22)