What's the real story on SOURCE v/s DRAIN trimmers in JFET circuits?

[stm]

Since some time the use of a source trimmer instead of a drain trimmer to bias JFET class-A amplifiers has been gaining adepts.  I would like to ask the promoters of this technique what are the actual facts that support SOURCE over DRAIN bias adjust.

So far the arguments I've seen are oriented to demean those using drain trimmers with arrogant statements like comparing drain biasing to a "parlor trick" or referring to source biasing as "what the skilled technician would do".  Of course none of us want to do a "parlor trick" in a guitar pedal intended for our personal use, and we all want to be compared to a "skilled technician", so +1 to the marketing dept.  This campaign has been quite effective, as the other day a "DIY veteran" referred apologetically to his use of drain trimmers as they still did the job.  And heck they do the job!

Perhaps the drain trimmer got a bad reputation since some DIY circuits have poorly chosen drain trimpots which either make the adjustment too difficult (if the trimpot is too large), or impossible (if the trimpot is too small).  This reasoning does not favor the use of a source trimmer, as a poor choice of the source trimmer and/or fixed drain resistor can produce equally ill results.

What next? Something evident is that as a drain trimpot is adjusted, the output impedance of the JFET stage varies accordingly, and so changes the frequency response due to the loading effect of following capacitors, to say the least.  OK, this seems like a good argument.  But the valve circuits that usually inspire JFET circuits all have large output impedances, in the range of 30k to 200k (by the way, the actual output impedance of a triode stage is a value SMALLER than the plate resistor, something typically between 1/3 and 2/3 the plate resistor, depending on the operating point).  So, having some output resistance is not bad after all, in fact you actually NEED IT so those tone control capacitors tied directly to the drain (or plate) behave as expected.  Ergo, what we would like is to have a fixed output resistance when a drain trimmer is used so as to have a repeatable and well-defined behavior...

...And it can be done. Rearranging a couple of wires around the trimpot you can have CONSTANT output impedance equal to the total trimpot value regardless of the trimpot's rotation.  The change is pretty obvious, yet I have never seen it used or mentioned before, so I decided to call it "stupidly wonderful drain biasing" or SWDB, following Mark Hammer's philosophy when naming his "stupidly wonderful tone control" or SWTC.

So, this is my newest "parlor trick": http://www.aronnelson.com/gallery/main.php/v/STMs-Circuit-Ideas/SWDB.png.html

After these arguments I see both biasing methods are tied, unless there is something else I am missing.

[dschwartz]

i just hate when someone comes up with this kind of ridicously simple solutions..makes me feel dumb!!!!

sebastian...la cagai pa seco!!! maestro!!! 

[petemoore]

  That looks like an elegant approach.
  Depends on the JFet, and what kind of gain structure you want, if the source resistor stays the same and the drain resistor gets huge to bring bias into focus...the gain of course will have been altered.
  ...A small handful of your favorite Jfets...a drain trimpot.
  A trick I liked...start with larg-ish source R, make long-leg version above board, then tack on a pot or a larger resistor on it [parallel reduces the R]...then get it biased and be able to better control the gain structure.
  Some schematics I believe actually press the Jfet into a 'corner' [for the effect that has] and some Jfets refuse to bias like that, numerous Jfets may not bias there...
  You can get your last Jfet to bias, one way or another...
  But I just pulled 3 transistors with 3 trimpots from an amp thing I built and tweeked and cajoled into working different ways this year [plenty of bias diddling, and put them in Mu amps...the rest of that amp-thing build had it's wires clipped so the board would come right out. This has happened numerous times.
 The Mu Amps biased right up, N/P 

[R.G.]

Changing the drain resistor changes the DC bias point and gain.
Changing the source resistor changes the DC bias point and gain.
Changing the gate voltage changes the DC bias point. You can't change the gate current except by sacrificing all gain on positive swings.

The impedance of the drain is somewhat immaterial - just ensure that what follows it is greater than 10x the drain impedance worst case. If you can't do that, use a buffer.

The real story is that JFETs vary. Learn the variations for the parts you use, and design to make the variations not matter, or tune per device. It makes no sense to say that tweaking source, drain or gate is better than the rest UNLESS YOU CAN ARTICULATE WHAT EFFECT THE CHANGE HAS ON THE REST OF THE CIRCUIT CONNECTED TO THE JFET.

[DougH]

Let me get this out of the way first- Re. people being "demeaned" for using a drain trimmer instead of a source trimmer- I haven't seen it. I mentioned the source trimmer a couple times as a "possibly better hack" for reasons that will follow. I referred to the drain trim as a parlor trick one time, but that had less to do with the particular technique and more to do with a general attitude I perceived at that time. I don't really care what techniques people use as long as they are happy with their results. This is not a manufacturing forum but a hobby forum so although consistency is a great design goal, it's not absolutely necessary. We already pre-select bjts and etc for other circuits that do not account for device variations in their design. But it does bother me when I see people being encouraged to settle for the status quo and not think outside the box because it's "too hard". It also bothers me to see someone go to the trouble to answer a question in detail, only to have it ignored or fluffed off. With enough of that, people will quit answering questions. Without people answering questions you have no forum.

Now back to the real subject - Changing the resistance of the drain circuit changes the gain, which is IMO more of a problem than output impedance changes (which can still be a problem too). Gainwise- changes in the source resistance due to using a source trimmer can be "masked" somewhat by using a) large bypass caps on the source that go to ground, or b) large bypass caps that go to an RC combination that goes to ground. The RC combination can be used to tune a HPF freq shelf, much like in a cathode circuit of a tube circuit. This works within limits- only if the source biasing trim is set high enough to have a negligible effect on the "R" in the RC circuit. If you use large drain resistors (100k for example), this helps keep the necessary source resistance high enough to reduce the effect it might have on any RC tuning.  If you just try plugging & playing tube amp topologies into it you will find other limitations with it as well. It's just a hack, but it worked well for some J201's I tried it with. I have not tested it across a large number of J201's or other JFET types.

There is no free lunch with any of these techniques. In the end, if you are building a one-off and you are happy with how it sounds using drain trimmers or whatever- none of this matters. The issue comes up where you want to design things that are repeatable and sound consistent. We've gotten to the point with bjt's and op amps that we can design stuff that sounds fairly consistent from one build to the next. It would be nice to find a way to do that with JFETs too.

IMO, the best way to mimic the sound of a particular amp is to do some analysis of the amp in question with a scope and spectrum analyzer. Then pick your building block of choice and start from scratch, much like LXH2 with the marshall/fender sim, or the German gentleman (can't remember his name) did with the AC30. Note they both used op amps as their building blocks because they are consistent and results are repeatable. I suppose you could follow a similar procedure with JFETs but you would need to use biasing techniques that take the JFET variations into account if you wanted repeatable successful results. Then again, IME it's just a heck of a lot easier to build a tube amp...

[earthtonesaudio]

I seem to keep coming back to constant current bias.  As long as you keep I_D lower than I_DSS, then I_D becomes independent of the JFET.  In practice it's really not hard to do.  The only reason not to is the extra transistor required, but that's still cheaper than a trimpot.

[DougH]

Yes, we discussed that in another thread Alex.

It's next on my list when I get back to the breadboard. I'm looking forward to trying the ideas you and others have tried from AN102!

[dschwartz]

IMHO, one thing i like about fets is the fact that they vary..IME, for fet versions of tube amps, the variations are small (i allways end up setting the trimpots at the same position for all fets, by ear) so i don´t think variations in fets are too significative..

i´ve built about 6 or 7 jfet preamps (dual rectal) and i´ve founmd that far more important is the choice of filtering values that fet biasing,. Although all preamps i made sound a little different, i found that they are as consistent as any tube amp..IMO Tubes are far less consistent than jfets , it depends on the brand, the hours used, how old they are, the outlet voltage, even two identical tubes may not sound the same.

So i like that "unpredictability" about jfets. The results are always good, but from time to time you get a fantastic device, just like with tubes, and even guitars!!..

As dougH said, if we want consistency, we should go with opamps, but there is something about fet´s tone that just doesn´t let me go back to opamps..for me, jfets are the ultimate tube equivalent, not because how they sound, is because what they MEAN..

[stm]

i just hate when someone comes up with this kind of ridicously simple solutions..makes me feel dumb!!!!

sebastian...la cagai pa seco!!! maestro!!! 

Hola Daniel.
Don't worry, when Mark Hammer came up with the SWTC I felt dumb too
You are "seco" too. You've done a terrific job with those hot rod dual rectos and valve amps! 

[dschwartz]

i just hate when someone comes up with this kind of ridicously simple solutions..makes me feel dumb!!!!

sebastian...la cagai pa seco!!! maestro!!! 

Hola Daniel.
Don't worry, when Mark Hammer came up with the SWTC I felt dumb too.
You are "seco" too. You've done a terrific job with those hot rod dual rectos and valve amps!

thanks.. although my approach is a bit more amateur-ish, all this "Ids, Igs, Zdgs, Abc, tick tack toe" still hits me in the face, and makes me think "what the heck..i´m going for the parlor trick!!"

about the discussion about technical info v/s "tricks":

My POV is that knowledge is a tool, sometimes you don´t need special tools for some jobs, you can make it work with a wrench, a screwdriver and a pair of scissors. The need for more sofisticated tools grows when we start to feel that the basic tools are not enough to get us where we want to go. If we are getting what we want with what we have.. Great!! why bother getting better tools?..Some people, anyway, are more interested in tools, wich is great, they strech the boundaries and produce new, better tools.

But the real wisdom is "how" we use those tools..some people can make marvels with just a wrench.. others need special tools for the same job, both are valid, but the investment is different

[Ben N]

Thanks for the cool innovation, Sebastian, and for clearing the air. I just want to point out that where this came up was in a thread about using the Tillman preamp as a booster, so in that context the issue of comparing jfet z-out to tube z-out is moot, and variation in output impedance caused by biasing certainly does affect the usefulness and predictability of the circuit in real-world applications. Of course, you seem to have addressed that problem now.

CCS really does seem to be a woefully unexplored area, with a lot of potential upside--and there is plenty of tube pedigree for that.  

Ben

[Gus]

The gain change is my  primary argument.

I do not depend on a small trim pot wiper for long term stability .  FWIW If you look at older lambda power supply often the current limit and voltage adjust trims are full size pots with good wipers and resistive track.

Next will there be enough Id?

Next look for the 80's solid state harvard schematic.   Note the source leg.

I don't post circuits I use with fets  I am aware of CC

Then there is input and output headroom.

I think a "good" design for a paint by number build should include a selection process for the fet(s) used.  Fets don't cost that much and you can sort them with simple homemade testers for what is built here.  People select transistors for FFs why not Fets.

When the "designer" posts a fet design maybe post reading like Vgs off and IDSS at a certain voltage of fet(s) they liked.

I am aware of CC I use it in some of my builds, that's why I posted links and posted about the neumann and Oktava circuits and to read the ANs.  "Designers" need to make the next step IMO.

[stm]

In answer to Doug's 5th post in this thread:

JFETs just have too much spread to try to pretend to find a trimless way of biasing ANY device in a given family.  For instance, a J201 may have a VgsOFF from -0.3 to -1.5 according to the datasheet, covering a 1:5 ratio.  There is no practical way of squeezing the lowest gain device so as to have as much gain as the highest gain device in the family. So, if uniform gain is a design goal one has to accept that gain will have to be leveled downwards.  Regarding Siliconix AN102, gain is leveled and the drain is properly biased, but other aspects of are sacrificed in the process, such as the simmetry and output dynamic range, which when used as a clipping device does have an audible effect.  Also, as the operating point in terms of the percentage of IDSS varies widely according to the device in use, the resulting harmonic structure is different also, which also makes an audible difference.  I have verified this in several simulations including vendor supplied models and JFET models adjusted for given values of VgsOFF and IDSS.  Of course AN102 method is excellent for general audio applications and for mass production, but for guitar audio I'd still rather have trimpots.

To complement the above, I'm not a fan of source bypass capacitors in JFETs. Yes, they do help to get more gain out from a particular stage, but at the same time they increase the 2nd harmonic content to a point where it becomes too noticeable for my personal taste.  In other words, the square-law (or approximately square-law) of the JFET becomes "too evident" due to the reduced voltage feedback via the source resistor.  I can support this last statement with many many listening tests at the breadboard--and I don't consider myself a golden ear, so if I can notice the differences it's beacause they are pretty evident!  Of course the cathode bypass capacitors in a valve stage are another story, since valves follow a milder three-halves current transfer law which is more bening in terms of  the harmonics that are introduced when the triode is running in the "linear" region.  Bottom line here is that a JFET behaves more like a triode in terms of the harmonics produced when it doesn't have a source bypass capacitor, and this is the essence of the Fetzer Valve.

As some may have noticed, the "revised" ROG circuits have been following such trend.  For instance, when designing Thor no source capactors were used, and circuit values were adjusted by ear to attain the target sound, rather than blindly copying the amp's values.  The output filter stage which boosts bass and cuts highs with a steeper 2nd order slope was tailored specifically to achieve the intended goal, yet it has nothing to do with the amp schematic, but rather to a desired functionality: emulating the 4x12 resonant peak and filtering highs.

Then again, when working on the Supreaux Deux (S.D.) no source bypass capacitors were used and the supply voltage was increased to for more gain and improved dynamic response. The high frequency filtering in the original Supreaux (after 1st stage and 2nd stages) didn't match that of the amp because the output impedance of the triodes was an integral part of the circuit, yet it was not considered.  We did extensive simulations and breadboard experiments to determine the actual operating impedances and cutoff frequencies.  As a result, resistors in series with the drain outputs were included to match the frequency response, however we still deviated from the original tone capacitor value (1n5 instead of 5n) based on what sounded better for our ears.  Now the S.D. sounds much closer compared with the real amp, but of course JFETs and triodes will never be the same, so there is no claim in that respect

Regarding the AC30 Sim, the author is Stephen Möeller (hope I spelled it right).  He certainly did a great job making a repeatable stage-by-stage opamp implementation of an AC-30 by copying the transient response derived from a sinusoidal burst with exponential decay.  I understand he licensed his design, but I am not aware of a commercial product derived from it.

[DougH]

Sebastian, I read your "new and improved Fetzer valve" article.

Where do these two equations come from?

Vd = 0.6*Vcc + 0.7*|Vp|

Rd = 0.9 * (Vcc - 2*|Vp|) / Idss

In particular I don't see where the .6 and .7 coefficients come from in the first equation.

[slacker]

For the idiots among us, please can someone explain how Sebastian's method keeps the output impedance constant?

I think I understand how the portion of the trimmer between the drain and vcc affects the output impedance, because assuming vcc is at AC ground then it's basically a resistor to ground, which I can get my head round, or is that wrong?
I can't figure out how this interacts with the portion between the drain and the output to keep the impedance constant though. I've tried visualising it taking into account the input impedance of a following circuit, but that doesn't help.
Do you have to factor in the effective resistance/impedance of the fet and source resistor or something?

I've obviously got a big hole in my knowledge, I'd be grateful if someone could fill it, or at least give me some pointers

[Ben N]

Hmmm... At one end of the trimpot's rotation, R_DS + RS are in parallel with RD; at the other end they are shorted out (w/re. output) and you have only RD. Is that right? If so, count me among the idiots (a place where I feel entirely comfortable  ).

[stm]

For the idiots among us, please can someone explain how Sebastian's method keeps the output impedance constant?

I think I understand how the portion of the trimmer between the drain and vcc affects the output impedance, because assuming vcc is at AC ground then it's basically a resistor to ground, which I can get my head round, or is that wrong?
I can't figure out how this interacts with the portion between the drain and the output to keep the impedance constant though. I've tried visualising it taking into account the input impedance of a following circuit, but that doesn't help.
Do you have to factor in the effective resistance/impedance of the fet and source resistor or something?

I've obviously got a big hole in my knowledge, I'd be grateful if someone could fill it, or at least give me some pointers

Hmmm... At one end of the trimpot's rotation, R_DS + RS are in parallel with RD; at the other end they are shorted out (w/re. output) and you have only RD. Is that right? If so, count me among the idiots (a place where I feel entirely comfortable  ).

When the JFET is operating in the so-called saturation or constant-current region, the output impedance is equivalent to the resistor installed between the supply and the drain terminal, named RD for this discussion.  This is because the JFET is acting as a current source, and ideal current sources have infinite resistance by definition.  So, this leaves RD with an infinite resistor to GND in place of the JFET, thus equivalent output resistance is just RD.

Disclaimer: In the real world, the equivalent resistance of the JFET is in the order of hundreds to thousands of kilo ohms instead of infinity, but for all practical purposes it is many times larger than RD so it can be disregarded.

Now in relation to the SWDB configuration, consider the trimpot as two resistors connected in series. Let's call RDa the part that acts as the new supply to drain resistor, and RDb the part that goes in series from the drain terminal of the JFET to the output terminal.  From the previous explanation, the impedance at the drain terminal is RDa, and since RDb is in series with it, the total output impedance is RDa+RDb, which is a constant value as RDa and RDb are part of the same trimpot.

Hope it makes sense!

[slacker]

Yes that makes perfect sense, thanks.

What I was doing was looking at the signal on the drain not the output. So I was thinking the impedance would have been RDa || (RDb + the impedance of what ever it was driving) That's why I couldn't see how it was constant.

[stm]

Sebastian, I read your "new and improved Fetzer valve" article.

Where do these two equations come from?

Vd = 0.6*Vcc + 0.7*|Vp|

Rd = 0.9 * (Vcc - 2*|Vp|) / Idss

In particular I don't see where the .6 and .7 coefficients come from in the first equation.

At the time the revisited Fetzer Valve article was prepared over two years ago, those coefficients were found empirically by simulations with JFETs with different values of VP and IDSS, so as to satisfy the following criteria:

1) RS=0.83*VP/IDSS (according to Danyuk's paper)

2) Drain voltage (output voltage) just reaches 2*VP when input voltage is +VP, which is just the point where the JFET leaves the constant-current region.  Since an input voltage of -VP produces drain current just to become zero, a simmetrical clipping-free input range from -VP to +VP is obtained.

This was further verified in the breadboard using J201's, 2N5457's and MPF102's with different values of VP and IDSS.

Of course this proofs nothing, so now I also have the full mathematical derivation of the equations that allow determining said coefficients for ANY biasing point, not just RS=0.83*VP/IDSS, where the quiescent drain current is expressed in terms of a percentage of IDSS.

We are about to release an article at the 'groove site with all the math behind. It is currently in the revision stage.

[JDoyle]

As this appears to be most likely directed at me, I will 'arrogantly' assume that the gauntlet has been tossed and skip the niceties entirely:

- 'Arrogance' is showing an unwarranted importance out of overbearing pride. How can stating a proven scientific fact, no matter how forcefully, be 'arrogant'? The CORRECT use would be to say that it is arrogant to assume that because what you are doing 'works', according to your own definition of 'works', it supersedes proven scientific fact.

- I never called a trimmer on the drain a 'parlor trick', I called it wrong. No need for 'marketing' any other version in when compared to that.

- How do you know a drain trimmer 'does the job' in a circuit, if by simply adjusting it you completely change the circuit's 'job' entirely?? In fact, with each twist of the trim you change the entire circuit itself.

- JFETs don't follow a strict 'square-law'. See Shockley's proof. The 'square-law' just happens to be a good approximation. This goes even more so for short channel JFETs like the J201. A MPF102 is probably closer to a square law approximation than any other of the 'common' JFET types normally used in FX.

- Qualifying designs through limiting the operation of the JFET, and the subsequent formulas used, to only the saturation region is convenient, but is simply not in the slightest bit realistic for our purposes. Unless a JFET stage is used EXCLUSIVELY to be as 'clean' a boost as possible, which, as we are talking about JFETs used in distortion circuits, ain't the case, one HAS TO consider the operation of the JFET in the ohmic region. To ignore this is to limit one's study of the distortion created in a JFET to the hard clip that occurs against the source resistor and completely ignores the 'squashing' that occurs when the signal causes the JFET to operate in the ohmic region - in my opinion the entire raison d'etre for using JFETs in the first place - why the hell else deal with the characteristic spreads that are at the core of this entire 'discussion' and the nightmare that is JFET design?

- Changing the resistance in the drain changes the gain of the stage. Period. I couldn't care less what the value of the trim actually is - though the end user certainly will as it is one entire half of the gain equation (Av=gm*Rd; Rs bypassed); and as JFETs vary so much, it is virtually guaranteed that in order to get the same voltage on the drain as that stated in the original design, the trim will have to have different values for separate, but conceptually identical, circuits. Therefore the gain of the circuit built by the designer will almost assuredly be quite different from the gain of another stage built by someone else, even though they are using the same part number and the exact same circuit. Put it this way - if it so happens that they DO match and the values are the EXACT same for the same bias condition in each case, that's the day someone needs to buy a damn lottery ticket.

- Setting Vgs to that suggested in the Fetzer Valve article to achieve the triode 'three-halves' transfer curve is great - until you apply a signal at the gate and completely change the bias relationship that got you to the three-halves situation in the first place. Because it is set to operate in the saturation region, and never in the ohmic region, Id is controlled exclusively by Vgs, Vds has little to no effect. Because of this, the standard Vgs vs. Id transfer curve (instead of the Vds vs. Id with plots for varying Vgs) is the relationship between Vgs and Id. So unless the coefficients presented are able to physically change the transfer curve, you still have the same JFET transfer curve, not a triode transfer curve, and still have a JFET amplifier. Also, even if Danyuk's paper is entirely correct, and everything works exactly as stated, all that is achieved is a linearly operated JFET simulating a linearly operated triode - which may be great for those hi-fi folks still hanging on the tubes but sick of getting shocked, but it is absolutely useless to a guitarist seaching for even the minimum amount of distortion - at some point, the signal HAS TO clip, or at the very least enter the ohmic region, for that type of distortion to occur, and it is at that exact point the entire reason for setting up the bias according to Danyuk is nullified.

- I never advocated a trimmer on the source, in fact, I never advocated anything except that a trim in the drain to adjust the quiescent drain voltage is wrong.

- One difference between this 'parlor trick' and the standard drain trim 'parlor trick' (please note that these are not my words or phrases, I'm using them for continuity) is that in this situation, unless the resistance of the trim is maxxed, you are immediately adding noise through series resistance, as well as attenuating the signal through voltage division between the portion of the trim from the wiper to the load and the load itself - the signal passed to the next stage, no matter what that stage is, occurs at the juncture between the two. Admittedly, if the load is high, such as a buffer or another FET stage, the attenuation is small, but the added noise won't go away. If the next stage is a BJT common emitter amplifier, chances are, there will be a fair amount of attenuation in addition to the noise, with the end result being a reduction in the S/N ratio even if any loss of gain is made up by the BJT stage.

- The portion of the trim between the wiper and the load adds to the load, being in series with the load, changing the effective drain resistance as the two together (the resistance from the wiper to the load and the load itself) are in parallel with the portion from the wiper to V+. So in this case not only are you changing Rd, the physical resistance between Vdd and the drain, but you are also changing the effective load on the stage at the same time, which also changes the effective drain resistance. This also limits the JFET stage's ability to charge and discharge any following stage's Miller capacitance reducing the frequency response and changing the way the following stage reacts to clipping - which will be slightly different at every setting of the trim and therefore another variable has been added, making the circuit even harder to replicate.

- The way to properly bias a JFET stage from a single voltage supply while keeping the gain structure as replicatable as possible is via Vgs - and there is a very old 'parlor trick' that does just that with a minimal amount of fuss. Biasing via Vgs does introduce the mirror issue of differences in gm from JFET to JFET, which are at the heart of the variation between single JFETs. However, the effect of gm variation between JFETs of the same type is less than that of physically varying a multiple kiloohm Rd, all other things being equal. Nothing is going to be perfect, especially with JFETs, or, as R.G. said, we would see a lot more JFET based consumer equipment.

Regards,

Jay Doyle