What's the real story on SOURCE v/s DRAIN trimmers in JFET circuits?

[stm]

>Aron, I think what needs to happen is we need to establish some criteria for pre-selecting the FETs. This could be like schematics where people note recommended hfe for bjt xsistors and so forth.

That's great.

Now how far are we going to take this? Are we going to insist that people measure their caps and posts and resistors BEFORE posting so that people can get repeatable results? How about cap types and brands since it does make a difference and the differences can be quite striking?

Where do we draw the line. It's like notation - not even close really.

Aron

Aron, I think the ideas expressed by Gus and Doug about accompanying schematics with JFET values and pre-screening JFETs when building the circuit represent a good compromise solution to JFET variation.  Pretending that ANY JFET in a given family should work *optimally* in a given circuit is asking too much, at least with the current knowledge and understanding of JFETs.

The latest circuits at ROG (Thor, Supreaux Deux) have been designed using "average" JFETs, according to the values in the table shown in Section 11 of the Fetzer Valve article in an attempt to maximize the probability of success for the builder.  But there is still room for trouble if a particular JFET is too far apart from the "average" value of its family.  This is where the proposed screening would enter: by including in the schems the range of values for VP and IDSS where the circuit is intended to work as expected, for each different type of JFET.  So, the builder would have to verify if the JFETs being used complies or not with the requirements using a simple JFET tester.

I don't think the above would allow avoiding trimmers, but at least it would make results far more predictable.

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Regarding your concern about extending this screening procedure or requirement to other components such as capacitors, I think that would be much over the top.  I'll venture to speak like Mark Hammer and give a metaphor to illustrate this:  properly choosing a JFET would be like the process of making wine, where the JFET spread would mean getting grape juice, wine or vinegar.  We just want wine.  Choosing different cap types, or even CC resistors v/s metalfilms would be more like using Carmenere, Cabernet Sauvignon or Merlot grapes; inevitably some people will prefer one or the other, but they all produce red wine in the end.

[frank_p]

Where do we draw the line.

Aron

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There ?  Was that conscious ?

[aron]

>I don't think the above would allow avoiding trimmers, but at least it would make results far more predictable.

Now my question is, what started this? Was there a rash of people complaining about their JFET projects any more than people complaining about Fuzz Face issues? Just wondering. As much as a "hack" the drain trimmer was, it allowed me to create many JFET projects with good results. When I built 2 or 3 op amp projects, they still sounded different from each other (no doubt due to caps and pot variation I assume). I do remember problems a while ago with the old MPF102 and even some J201, but with the Fairchild and Siliconix, the large variations have long gone for me in terms of getting a JFET sounding circuit to sound good.

[DougH]

>Aron, I think what needs to happen is we need to establish some criteria for pre-selecting the FETs. This could be like schematics where people note recommended hfe for bjt xsistors and so forth.

That's great.

Now how far are we going to take this? Are we going to insist that people measure their caps and posts and resistors BEFORE posting so that people can get repeatable results? How about cap types and brands since it does make a difference and the differences can be quite striking?

Where do we draw the line. It's like notation - not even close really.

Aron

Actually, it's not a bad idea to measure resistors before building, even though I don't do it. I hear amp guys insist all the time that you measure resistors before installing, due to the possibility of reading color codes incorrectly, tolerances, etc.

To me, the point of specifying criteria for a JFET is to basically get the circuit to bias up correctly. Then you could build the circuit with fixed resistors and it would pretty easy to get circuits that consistently work. It would also make the gain of the circuit consistent across builds. Cap types and so forth I view as a secondary "taste" consideration.

[DougH]

>I don't think the above would allow avoiding trimmers, but at least it would make results far more predictable.

Now my question is, what started this? Was there a rash of people complaining about their JFET projects any more than people complaining about Fuzz Face issues? Just wondering. As much as a "hack" the drain trimmer was, it allowed me to create many JFET projects with good results. When I built 2 or 3 op amp projects, they still sounded different from each other (no doubt due to caps and pot variation I assume). I do remember problems a while ago with the old MPF102 and even some J201, but with the Fairchild and Siliconix, the large variations have long gone for me in terms of getting a JFET sounding circuit to sound good.

I think what started it was people recognizing that there's probably a better way of doing this so hey, let's explore it.

[aron]

>I think what started it was people recognizing that there's probably a better way of doing this so hey, let's explore it.

Now that is _cool_. But I cannot help but think that for some reason this discussion got a lot more heated and debated than something like stacked transistors or stacked op amps.

In any case, a LOT of useful info was posted IMO.

[stm]

We have updated the JFET Tester in a Fetzer Valve article with a more user-friendly version that is simple to build as a tool for measuring IDSS and VP fast and easy by flipping an SPDT switch.

http://runoffgroove.com/fetzervalve.html#11

[petemoore]

  That's enough to make me want to build the tester, and figure out the power supply and then build around some Jfets !.
 

[John Lyons]

Cool! thanks for the work on this.

john

[frank_p]

Great ! Thanks !

[Gus]

I think this thread was a good one.

[DougH]

The reason I was asking about whether you used a source bypass cap is because in your experiment where you compared gains by varying the size of the source resistor, you didn't take into account the degenerative feedback that the resistor contributes. And yes, that will make the gain vary quite a bit depending on that resistor size.

Both the simulation (done using Microcap 7 for Transient and AC Analysis) and the algebraic analysis do include the effect of the degenerative feedback introduced by RS.  Proof of this is that the gain equations do include the RS term in the denominator, and as RS increases gain reduces by virtue of the degenerative feedback.

Well, okay I guess my point is that if you are claiming that varying source resistance in an unbypassed source circuit will affect gain, I agree completely, mainly due to the effect of the degenerative feedback. But are you claiming that varying the source resistance in a bypassed source circuit affects gain as well? It's not clear to me if that's what you are claiming as well.

[stm]

Varying source resistor WITH or WITHOUT source bypass capacitor changes the gain.

Here I posted the gain formulas for each case:

http://www.diystompboxes.com/smfforum/index.php?topic=70065.msg563089#msg563089

The bypassed gain is higher of course, but it still depends on the quiescent or steady-state DC drain current, which is set solely by RS and the JFET parameters IDSS and VP, as at DC the effect of the bypass capacitor is null.  Then, when signal is applied, the effect of degenerative feedback by means of RS disappears because of the source bypass capacitor, but gain is was already subject to the DC operating point.

I have confirmed this by:

a. Developing the mathematics behind (which lead to the formulas presented in the link above)
b. In simulations
c. In practical circuits at breadboard level.

Best regards,

Sebastian

[alanlan]

Of course, changing Rs alters the bias point and with it the gain at that point on the transfer characteristic but it is important to realize that the gain is only constant in the small signal sense.  With Rs bypassed, vgs sees the full input swing and therefore the gain is dynamically varying and with it, adding the characteristic increase in 2nd harmonic distortion. 

[Eb7+9]

alanlan's got it, there's a need to understand why zero-crossing numbers (short-cut math stuff) are replaced by curves in the greater scheme of things ... indeed, in that realm Rs chiefly regulates the harmonics producing transfer curvature of the transconductance stage through the action of local Negative Feedback ... in his paper Dannyuk sets Rs to match the Harmonic Distortion profile of a test triode for his jFET circuit (his goal) while also setting bias current in the process ... note that with higher current you get more noise for one, and as you drop Rs you also lose headroom ...

Vd plays a secondary role in establishing drain current - up to saturation limits of course, and so the same goes of Rd once Id is set by Rs and rough Vd values ... in other words you can spare yourself production head-aches by selecting Rd at a good average value and putting a trimmer at Rs - even if you don't know your likely worse-case Vgs(off) and Idss spreads this will work well for biasing single-ended gain stages with ease ...

for matching and spec'ing there is no choice but to follow a proper Idss & Vgs(off) test and match them to a reference data-pair if predictable results are required - this is even more important in VCR applications because of the super high sensitivity around Vgs(off) ... if you play with these variables carefully you can build a reliable true-schematic emulation of the Fender Vibrato and Tremolo circuits ...

pictures @11

[stm]

Vd plays a secondary role in establishing drain current - up to saturation limits of course, and so the same goes of Rd once Id is set by Rs and rough Vd values ... in other words you can spare yourself production head-aches by selecting Rd at a good average value and putting a trimmer at Rs - even if you don't know your likely worse-case Vgs(off) and Idss spreads this will work well for biasing single-ended gain stages with ease ...

It is better to select RS at a good average value and trim RD instead.  If RD is wired as proposed at the beginning of this thread (SWDB method), then output impedance will remain constant.  Link here: http://www.aronnelson.com/gallery/main.php/v/STMs-Circuit-Ideas/SWDB.png.html

I explained before with practical data why tuning RD should be preferred over tuning RS to set the operating, which I reproduce here for clarity:

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I used three J201's: specimen A with Vp=0.5V and Idss=0.1mA, specimen B with Vp=0.8V and Idss=0.24mA, and specimen C with Vp=1.2V and Idss=0.4mA.  They are pretty representative of low, medium and high VP's.

First, I biased the three JFETs according to the Fetzer Valve values using RS equal to the recommended value for the middle device (1100 ohms), and tuned the drain trimmer to the recommended drain values of 6200, 10900 and 22000 ohms.  Gains obtained were: 10, 14 and 19 dB, respectively.

Second, I changed the drain resistor for the recommended value for the middle device (10900 ohms), and tuned the source trimmer so as to obtain the recommended drain voltage (same as in the first part).  Required source trimmer values were: 2430, 1100 and 180 ohms, respectively.  And gains obtained were again 10, 14 and 19, respectively.  Decimal differences were less than 0.5 dB with respect to the previous case.

Conclusion: tuning with a drain or source trimmer under similar conditions in a controlled experiment produced the very same gains.  In each case the target drain voltage was chosen for maximum dynamic range according to the particular VP of each stage.

Moreover, drain trimmer resistor required only a 3:1 variation, while the source resistor required a 13:1 variation.  Imagine trying to accurately set 180 ohms for the last stage using a 5k source trimpot.  Very difficult indeed.

And not content with the above, I run the FFT analysis on each case, feeding each stage with its maximum clipping-free input signal, i.e. +/-VP.  The results showed that the 2nd harmonic in the drain trimmer case varied from 11.5% to 12% to 13.8%, while in case of the source trimmer it varied from 8.3% to 12% to 20.3% for the three specimens under test.  It is evident that the source trimmer affects greatly the 2nd harmonic and thus produces a much wider variation in sound than drain trimmer.

Based on all the above, I only see disadvantages in using a source trimmer over a drain trimmer.
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Of course, changing Rs alters the bias point and with it the gain at that point on the transfer characteristic but it is important to realize that the gain is only constant in the small signal sense.  With Rs bypassed, vgs sees the full input swing and therefore the gain is dynamically varying and with it, adding the characteristic increase in 2nd harmonic distortion. 

That's true. Just want to emphasize that even if the gain varies dynamically for large signals, overall gain is clearly affected by variations in the source resistor, whether with or without source bypass capacitor installed, as demonstrated by the following graph:



Blue curves correspond to the unbypassed case, and red curves correspond to the bypassed case.  One can readily see the gain increase when adding the bypass capacitor.  Also, the red curves exhibit some noticeable squashing at the tops when compared to the bottoms, which is the effect of the increased 2nd harmonic content.

[DougH]

>I think what started it was people recognizing that there's probably a better way of doing this so hey, let's explore it.

Now that is _cool_. But I cannot help but think that for some reason this discussion got a lot more heated and debated than something like stacked transistors or stacked op amps.

I think that had more to do with clashing personalities and attitudes in some other threads.

[DougH]

Just want to emphasize that even if the gain varies dynamically for large signals, overall gain is clearly affected by variations in the source resistor, whether with or without source bypass capacitor installed, as demonstrated by the following graph:

As I suspected, from your graphs the gain does not appear to vary as much in a circuit that has the source bypassed. But I don't always trust simulations. I'll have to play with this stuff on the breadboard to get a handle on what's going on.

Good info in this thread!

[stm]

I want to express an idea to see if it rings a bell:  the two *main* JFET parameters that define the response of a particular JFET are the gate cutoff voltage (VP) and the drain saturation current (IDSS).  At first glance one could say we have two degrees of freedom that need to be adjusted in a given circuit, so a *perfect* biasing scheme should require two trimpots (or choosing two resistors).  This is quite evident in the case of the self-bias method where the selection of RS and RD are both relevant to the final circuit behaviour.

Currently we have resorted to using a single trimpot or adjustment for either RS or RD, but as the drain voltage is adjusted, the operating point (in terms of drain current) is changed also, not to speak about gain and input dynamic range.

Further investigation show that for JFETs with the same part number, there is a definite and fixed relation between IDSS and VP.  This can be seen in graphic form in J201 and 2N5457 datasheets (Fairchild manufacturer, 3rd page).  In other words, when a datasheet indicates VP from 0.3 to 1.5, and IDSS from 0.2mA to 1mA, it doesn't mean you can have a JFET with any pair of VP and IDSS values withing those ranges.  These parameters are in fact "tied" by a definite relation, which is approximately IDSS=a*(VP^b), where 'a' and 'b' are constants that correspond to that particular device family.

The above means that there is in fact a single degree of freedom that differentiates one J201 from another. Now the question is, how do we take this to our advantage? The next logical step is to do a thorough analysis on mixed biasing methods, combining both gate voltage and self-bias.

[DougH]

Well, if that's correct, you have just reduced two handles down to one handle.

Now we just have to figure out how to grab hold of it.